From patchwork Sat Jul 24 08:18:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 1509446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=IInVGTfx; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWzcG5dDPz9sXN for ; Sat, 24 Jul 2021 18:19:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234842AbhGXHig (ORCPT ); Sat, 24 Jul 2021 03:38:36 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:26670 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234853AbhGXHif (ORCPT ); Sat, 24 Jul 2021 03:38:35 -0400 X-UUID: 66f4895c0d4b45ce8ae2212ca1067df7-20210724 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oz8R6JzK/dsLcXIYjmpTj+oBt2JJQ5u816nXyN6D10Q=; b=IInVGTfxFKK/kwhZh6NBWauSj7SH+RAMxhrDQxjLoAuFOr/MIWapDZ5uNQTlIcnXjWh0sFMVDmRch/hwFAcB0GrKGxc+hLdnfdVfLs0Hf9w9JnBbdd94v3yDspoGykawCOOw1B8M2uEegY7Ka3BLcRrQTECOAlt/r65ohM5nn0w=; X-UUID: 66f4895c0d4b45ce8ae2212ca1067df7-20210724 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 555332565; Sat, 24 Jul 2021 16:19:03 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 24 Jul 2021 16:18:55 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 24 Jul 2021 16:18:54 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 4/5] pwm: mtk_disp: fix overflow in period and duty calcalation Date: Sat, 24 Jul 2021 16:18:48 +0800 Message-ID: <20210724081849.182108-5-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210724081849.182108-1-jitao.shi@mediatek.com> References: <20210724081849.182108-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 00542DEEE62E7D67BBB1D34FA5DE6387FF294617A841F8A5F6153D1AF11FE15A2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Current calculation for period and high_width may have 64-bit overflow. state->period and rate are u64. rate * state->period will overflow. clk_div = div_u64(rate * state->period, NSEC_PER_SEC) period = div64_u64(rate * state->period, div); high_width = div64_u64(rate * state->duty_cycle, div); This patch is to resolve it by using mul_u64_u64_div_u64(). Signed-off-by: Jitao Shi --- drivers/pwm/pwm-mtk-disp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 599d7dd8ecab..4f6de6f24484 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -116,7 +116,7 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) */ rate = clk_get_rate(mdp->clk_main); - clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >> + clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> PWM_PERIOD_BIT_WIDTH; if (clk_div > PWM_CLKDIV_MAX) { if (!mdp->enabled) { @@ -127,11 +127,11 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, } div = NSEC_PER_SEC * (clk_div + 1); - period = div64_u64(rate * state->period, div); + period = mul_u64_u64_div_u64(state->period, rate, div); if (period > 0) period--; - high_width = div64_u64(rate * state->duty_cycle, div); + high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); mtk_disp_pwm_update_bits(mdp, mdp->data->con0,