From patchwork Sat Jul 24 08:18:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 1509443 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=u1/bbjuo; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWzc826D7z9sXN for ; Sat, 24 Jul 2021 18:19:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234778AbhGXHia (ORCPT ); Sat, 24 Jul 2021 03:38:30 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:18422 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234772AbhGXHi3 (ORCPT ); Sat, 24 Jul 2021 03:38:29 -0400 X-UUID: cc46317b093d4033b99c0da6cb7cafcc-20210724 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FqIjmHCwaupnBJmDHNq0CA3qx0xdA5LsYBCK0CPOTPY=; b=u1/bbjuom/N//cZgwgGzlKFnhqcGB7VXMcGU6ldupKgVUVYyyvRFYDnjPMdiO0+5D79zmo491GA363dkZyr57+GCpKUdQYPngPii8I5On/ByIEgzrStEnbalxEe2g2OZVaRJaKNotKZA43YBKfa2W9qXrMIWk79rW6FU3U4jfik=; X-UUID: cc46317b093d4033b99c0da6cb7cafcc-20210724 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1468019768; Sat, 24 Jul 2021 16:18:58 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 24 Jul 2021 16:18:53 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 24 Jul 2021 16:18:52 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 2/5] pwm: mtk_disp: fix force reg to working reg. Date: Sat, 24 Jul 2021 16:18:46 +0800 Message-ID: <20210724081849.182108-3-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210724081849.182108-1-jitao.shi@mediatek.com> References: <20210724081849.182108-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 67574F026B928C06B03282D42610A74070D813AB8F993D86C11FD52D507114AF2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Disable reg double buffer before writing register. Signed-off-by: Jitao Shi --- drivers/pwm/pwm-mtk-disp.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 3ade525adcc3..1070d78d4940 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -128,6 +128,17 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, mtk_disp_pwm_update_bits(mdp, mdp->data->commit, mdp->data->commit_mask, 0x0); + } else { + /* + * For MT2701, disable double buffer before writing register + * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. + */ + mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, + mdp->data->bls_debug_mask, + mdp->data->bls_debug_mask); + mtk_disp_pwm_update_bits(mdp, mdp->data->con0, + mdp->data->con0_sel, + mdp->data->con0_sel); } clk_disable_unprepare(mdp->clk_mm); @@ -213,19 +224,6 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, mdp); - /* - * For MT2701, disable double buffer before writing register - * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. - */ - if (!mdp->data->has_commit) { - mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, - mdp->data->bls_debug_mask, - mdp->data->bls_debug_mask); - mtk_disp_pwm_update_bits(mdp, mdp->data->con0, - mdp->data->con0_sel, - mdp->data->con0_sel); - } - return 0; }