diff mbox series

[1/6] pwm: sun4i: enable clk prior to getting its rate

Message ID 20210531044608.1006024-2-roman.beranek@prusa3d.com
State New
Headers show
Series pwm: sun4i: only wait 2 cycles prior to disabling | expand

Commit Message

Roman Beranek May 31, 2021, 4:46 a.m. UTC
Ensure the PWM clock is enabled prior to retrieving its rate, as is
already being done in sun4i_pwm_apply.

Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
---
 drivers/pwm/pwm-sun4i.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Uwe Kleine-K├Ânig June 7, 2021, 8 a.m. UTC | #1
On Mon, May 31, 2021 at 06:46:03AM +0200, Roman Beranek wrote:
> Ensure the PWM clock is enabled prior to retrieving its rate, as is
> already being done in sun4i_pwm_apply.
> 
> Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
> ---
>  drivers/pwm/pwm-sun4i.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index e01becd102c0..3721b9894cf6 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -117,8 +117,15 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>  	u64 clk_rate, tmp;
>  	u32 val;
>  	unsigned int prescaler;
> +	int ret;
>  
> +	ret = clk_prepare_enable(sun4i_pwm->clk);
> +	if (ret) {
> +		dev_err(chip->dev, "failed to enable PWM clock\n");
> +		return;
> +	}
>  	clk_rate = clk_get_rate(sun4i_pwm->clk);
> +	clk_disable_unprepare(sun4i_pwm->clk);
>  
>  	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

If the clock is off, does the PWM actually run? Assuming it doesn't the
right thing to do is to ensure the clock is enabled in .probe iff the
PWM is enabled.

Best regards
Uwe
diff mbox series

Patch

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index e01becd102c0..3721b9894cf6 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -117,8 +117,15 @@  static void sun4i_pwm_get_state(struct pwm_chip *chip,
 	u64 clk_rate, tmp;
 	u32 val;
 	unsigned int prescaler;
+	int ret;
 
+	ret = clk_prepare_enable(sun4i_pwm->clk);
+	if (ret) {
+		dev_err(chip->dev, "failed to enable PWM clock\n");
+		return;
+	}
 	clk_rate = clk_get_rate(sun4i_pwm->clk);
+	clk_disable_unprepare(sun4i_pwm->clk);
 
 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);