From patchwork Sat Jan 30 14:12:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 1433680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=aQMk6qXD; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DSbnq4WKqz9sVy for ; Sun, 31 Jan 2021 01:15:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231880AbhA3OOg (ORCPT ); Sat, 30 Jan 2021 09:14:36 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:59723 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231666AbhA3ONo (ORCPT ); Sat, 30 Jan 2021 09:13:44 -0500 X-UUID: fac2dfdd45ae48ccab3eadd4c5120212-20210130 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DyzlMt+ZRsFBAamZ/P7DPnw9Tzbiso9sA1OiSGy7Xek=; b=aQMk6qXDKIs6a9p3jtmaMOjMed+bTH1nJqB5brc5CQHQOuZct5GNvMlBay5qtgLmiOJgMhT24DurCbFGMGRo3RiBccstrePAp2IZEcw7u9NEsUNFuS7Y9iFaQKW/Ko/iUevzEJ8Nhrjr9ou0SdtXe5NzyXqk9QSXXrrMATKNNVg=; X-UUID: fac2dfdd45ae48ccab3eadd4c5120212-20210130 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 501370062; Sat, 30 Jan 2021 22:12:35 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 30 Jan 2021 22:12:33 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 30 Jan 2021 22:12:32 +0800 From: Jitao Shi To: Thierry Reding , Matthias Brugger CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH v2 3/3] pwm: mtk_disp: implement .get_state() Date: Sat, 30 Jan 2021 22:12:26 +0800 Message-ID: <20210130141226.25357-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20210130141226.25357-1-jitao.shi@mediatek.com> References: <20210130141226.25357-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 05FF14DABF24935074C7B5A197E4A8FAE17711D2C7A914C6F6F525F957A904C82000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Jitao Shi --- drivers/pwm/pwm-mtk-disp.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 502228adf718..166e0a8ca703 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -179,8 +179,54 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return mtk_disp_pwm_enable(chip, state); } +static void mtk_disp_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); + u32 clk_div, period, high_width, con0, con1; + u64 rate; + int err; + + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %d\n", err); + return; + } + err = clk_prepare_enable(mdp->clk_mm); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_mm: %d\n", err); + clk_disable_unprepare(mdp->clk_main); + return; + } + + rate = clk_get_rate(mdp->clk_main); + + con0 = readl(mdp->base + mdp->data->con0); + con1 = readl(mdp->base + mdp->data->con1); + + state->polarity = con0 & PWM_POLARITY ? + PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + state->enabled = !!(con0 & BIT(0)); + + clk_div = (con0 & PWM_CLKDIV_MASK) >> PWM_CLKDIV_SHIFT; + period = con1 & PWM_PERIOD_MASK; + state->period = div_u64(period * (clk_div + 1) * NSEC_PER_SEC, rate); + high_width = (con1 & PWM_HIGH_WIDTH_MASK) >> PWM_HIGH_WIDTH_SHIFT; + state->duty_cycle = div_u64(high_width * (clk_div + 1) * NSEC_PER_SEC, + rate); + + if (!state->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } + + mdp->enabled = state->enabled; +} + static const struct pwm_ops mtk_disp_pwm_ops = { .apply = mtk_disp_pwm_apply, + .get_state = mtk_disp_pwm_get_state, .owner = THIS_MODULE, };