From patchwork Tue Apr 16 08:54:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 1086140 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jzhs0tGwz9s70 for ; Tue, 16 Apr 2019 18:55:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728786AbfDPIzE (ORCPT ); Tue, 16 Apr 2019 04:55:04 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:56796 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726576AbfDPIzC (ORCPT ); Tue, 16 Apr 2019 04:55:02 -0400 X-UUID: 693e98bd81254991b05e96e47a91bcc1-20190416 X-UUID: 693e98bd81254991b05e96e47a91bcc1-20190416 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 196416271; Tue, 16 Apr 2019 16:54:56 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 16:54:54 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 16 Apr 2019 16:54:53 +0800 From: Jitao Shi To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , , David Airlie , Matthias Brugger CC: Jitao Shi , Thierry Reding , Ajay Kumar , Inki Dae , Rahul Sharma , Sean Paul , Vincent Palatin , Andy Yan , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , , Subject: [PATCH 2/2] arm64: dts: mt8183: add pwm0 node Date: Tue, 16 Apr 2019 16:54:46 +0800 Message-ID: <20190416085446.84071-3-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190416085446.84071-1-jitao.shi@mediatek.com> References: <20190416085446.84071-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add pwm0 node to the mt8183 Signed-off-by: Jitao Shi --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 80929a0e5a6f..2830008c4921 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -323,6 +323,17 @@ status = "disabled"; }; + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + }; + audiosys: syscon@11220000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>;