Message ID | 20180724231958.20659-20-paul@crapouillou.net |
---|---|
State | Superseded |
Headers | show |
Series | None | expand |
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 50cff3cbcc6d..700cf28a52ec 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -238,3 +238,9 @@ bias-disable; }; }; + +&tcu { + /* 3 MHz for the system timer */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>; + assigned-clock-rates = <3000000>; +};
The default clock (48 MHz) is too fast for the system timer, which fails to report time accurately. Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++ 1 file changed, 6 insertions(+) v5: New patch