From patchwork Sun Dec 6 11:32:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 553123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DD2881402BF for ; Sun, 6 Dec 2015 22:32:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753932AbbLFLcT (ORCPT ); Sun, 6 Dec 2015 06:32:19 -0500 Received: from mleia.com ([178.79.152.223]:51876 "EHLO mail.mleia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754170AbbLFLcL (ORCPT ); Sun, 6 Dec 2015 06:32:11 -0500 Received: from mail.mleia.com (localhost [127.0.0.1]) by mail.mleia.com (Postfix) with ESMTP id CEE6C117AAA; Sun, 6 Dec 2015 11:34:08 +0000 (GMT) From: Vladimir Zapolskiy To: Thierry Reding , Rob Herring , Arnd Bergmann Cc: Roland Stigge , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org Subject: [PATCH v2 6/6] pwm: lpc32xx: return ERANGE, if requested period is not supported Date: Sun, 6 Dec 2015 13:32:02 +0200 Message-Id: <1449401522-22590-7-git-send-email-vz@mleia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1449401522-22590-1-git-send-email-vz@mleia.com> References: <1449401522-22590-1-git-send-email-vz@mleia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-49551924 X-CRM114-CacheID: sfid-20151206_113408_869593_4542FD5D X-CRM114-Status: GOOD ( 14.05 ) Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Instead of silent acceptance of unsupported requested configuration for PWM period and setting the boundary supported value, return -ERANGE to a caller. Duty period value equal to 0 or period is still accepted to allow configuration by PWM sysfs interface, when it is set to 0 by default. For reference this is a list of restrictions on period_ns == 1/freq: | PWM parent clock | parent clock divisor | max freq | min freq | +------------------+----------------------+----------+----------+ | HCLK == 13 MHz | 1 (min) | 50.7 KHz | 198.3 Hz | | HCLK == 13 MHz | 15 (max) | 3.38 KHz | 13.22 Hz | | RTC == 32.7 KHz | 1 (min) | 128 Hz | 0.5 Hz | | RTC == 32.7 KHz | 15 (max) | 8.533 Hz | 0.033 Hz | Note that PWM sysfs interface does not support setting of period more than NSEC_PER_SEC / MAX_INT32 ~ 2 seconds, however this PWM controller supports a period up to 30 seconds. Signed-off-by: Vladimir Zapolskiy --- Changes from v1 to v2: - none drivers/pwm/pwm-lpc32xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index 294a68f..4d470c1 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -41,9 +41,9 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* The highest acceptable divisor is 256, which is represented by 0 */ period_cycles = div64_u64(c * period_ns, (unsigned long long)NSEC_PER_SEC * 256); - if (!period_cycles) - period_cycles = 1; - if (period_cycles > 255) + if (!period_cycles || period_cycles > 256) + return -ERANGE; + if (period_cycles == 256) period_cycles = 0; /* Compute 256 x #duty/period value and care for corner cases */