From patchwork Fri Jan 9 23:34:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 427295 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7058C140187 for ; Sat, 10 Jan 2015 10:37:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758316AbbAIXhV (ORCPT ); Fri, 9 Jan 2015 18:37:21 -0500 Received: from vps0.lunn.ch ([178.209.37.122]:49511 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758314AbbAIXhU (ORCPT ); Fri, 9 Jan 2015 18:37:20 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.80) (envelope-from ) id 1Y9j4y-0008FE-3I; Sat, 10 Jan 2015 00:34:56 +0100 From: Andrew Lunn To: linus.walleij@linaro.org Cc: Thomas Petazzoni , kaloz@openwrt.org, Gregory Clement , Sebastian Hesselbarth , linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org, Andrew Lunn Subject: [PATCH 4/7] DT: bindings: Extend mvebu gpio documentation with PWM Date: Sat, 10 Jan 2015 00:34:50 +0100 Message-Id: <1420846493-31647-5-git-send-email-andrew@lunn.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1420846493-31647-1-git-send-email-andrew@lunn.ch> References: <1420846493-31647-1-git-send-email-andrew@lunn.ch> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Document the optional parameters needed for PWM operation of gpio lines. Signed-off-by: Andrew Lunn --- .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index a6f3bec1da7d..9984e2665568 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -38,6 +38,23 @@ Required properties: - #gpio-cells: Should be two. The first cell is the pin number. The second cell is reserved for flags, unused at the moment. +Optional properties: + +In order to use the gpio lines in PWM mode, some additional optional +properties are required. Only Armada 370 and XP supports these +properties. + +- reg: an additional register set is needed, for the GPIO Blink + Counter on/off registers. + +- reg-names: Must contain an entry "pwm" corresponding to the + additional register range needed for pwm operation. + +- #pwm-cells: Should be two. The first cell is the pin number. The + second cell is reserved for flags, unused at the moment. + +- clocks: Must be a phandle to the clock for the gpio controller. + Example: gpio0: gpio@d0018100 { @@ -51,3 +68,17 @@ Example: #interrupt-cells = <2>; interrupts = <16>, <17>, <18>, <19>; }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; + clocks = <&coreclk 0>; + };