From patchwork Sat Jun 21 14:22:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 362433 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B37D114007D for ; Sun, 22 Jun 2014 00:24:36 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753190AbaFUOYA (ORCPT ); Sat, 21 Jun 2014 10:24:00 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:44213 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753531AbaFUOXs (ORCPT ); Sat, 21 Jun 2014 10:23:48 -0400 Received: by mail-wi0-f172.google.com with SMTP id hi2so2082522wib.17 for ; Sat, 21 Jun 2014 07:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tw+ioor+g4mt9fMRkR8Sp23dggRMYhQ7WGLSnXVAuuU=; b=Q1sGz2aorn1NyLLvML8boEV0cOy5KC7CvEWRRsvdTmAvr8VAe1ZmmqZADP5Snx0oAD 3ICHdrXDTwEqsJfXeguVifz4DpzIi+PZLLSYwNfm5mH3n4CZenkRZxbSgpo4Fmj48BnF 9OKIhtBcAgYdW3aWUiryzWDu+VFR8qFdEY1vN8SZYuem5pu7El6J8h4Yyv4K8SpdzS05 bFWwOO79BjuHPDO49RAoy0jSDwLCz5nBk0TzQOMv8T3BBojfaVeGSb9eOtUiKoJgXBYb 2a2bDfIswcFxPd6ka0raTL7w28EROfGcvjg+JypAntMc8kFdno0RMevhvuA4qq52ZGKK 4JuA== X-Received: by 10.194.11.74 with SMTP id o10mr12565267wjb.82.1403360627414; Sat, 21 Jun 2014 07:23:47 -0700 (PDT) Received: from sark.local (host188-27-dynamic.31-79-r.retail.telecomitalia.it. [79.31.27.188]) by mx.google.com with ESMTPSA id rw4sm22667978wjb.44.2014.06.21.07.23.45 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Jun 2014 07:23:46 -0700 (PDT) From: Beniamino Galvani To: Thierry Reding Cc: Heiko Stuebner , linux-pwm@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Beniamino Galvani Subject: [PATCH v2 3/3] ARM: dts: rk3xxx: add PWM nodes Date: Sat, 21 Jun 2014 16:22:08 +0200 Message-Id: <1403360528-12757-4-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1403360528-12757-1-git-send-email-b.galvani@gmail.com> References: <1403360528-12757-1-git-send-email-b.galvani@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This adds PWM nodes to the Rockchip device trees. Signed-off-by: Beniamino Galvani --- arch/arm/boot/dts/rk3188.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index a50a462..a91e205 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -114,6 +114,22 @@ clock-names = "biu", "ciu"; }; + pwm0: pwm@20030000 { + clocks = <&cru PCLK_PWM01>; + }; + + pwm1: pwm@20030010 { + clocks = <&cru PCLK_PWM01>; + }; + + pwm2: pwm@20050020 { + clocks = <&cru PCLK_PWM23>; + }; + + pwm3: pwm@20050030 { + clocks = <&cru PCLK_PWM23>; + }; + cru: cru@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; @@ -310,6 +326,30 @@ ; }; }; + + pwm0 { + pwm0_pins: pwm0-pins { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_pins: pwm1-pins { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_pins: pwm2-pins { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_pins: pwm3-pins { + rockchip,pins = ; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 2adf1cc9e..80811bb 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -135,5 +135,37 @@ status = "disabled"; }; + + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 10>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 10>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 11>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 11>; + status = "disabled"; + }; }; };