From patchwork Mon Apr 28 08:55:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Cross X-Patchwork-Id: 343308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 713A714133E for ; Mon, 28 Apr 2014 19:05:47 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754157AbaD1JFi (ORCPT ); Mon, 28 Apr 2014 05:05:38 -0400 Received: from mail1.g1.pair.com ([66.39.3.162]:52415 "EHLO mail1.g1.pair.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753604AbaD1JFg (ORCPT ); Mon, 28 Apr 2014 05:05:36 -0400 Received: from localhost.localdomain (unknown [210.23.18.184]) by mail1.g1.pair.com (Postfix) with ESMTPSA id 46C2F2C0EC; Mon, 28 Apr 2014 04:55:52 -0400 (EDT) From: Sean Cross To: Thierry Reding , Grant Likely , Rob Herring , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org Cc: Sean Cross Subject: [PATCH] pwm: imx: Support very long period lengths Date: Mon, 28 Apr 2014 16:55:31 +0800 Message-Id: <1398675331-10980-2-git-send-email-xobs@kosagi.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1398675331-10980-1-git-send-email-xobs@kosagi.com> References: <1398675331-10980-1-git-send-email-xobs@kosagi.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The IMX PWM block supports using both the system clock and a 32 kHz clock for driving PWM events. For very long period lengths, use the 32 kHz clock instead of the high-speed clock. Signed-off-by: Sean Cross --- drivers/pwm/pwm-imx.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index cc47733..8410455 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -36,9 +36,11 @@ #define MX3_PWMCR_DOZEEN (1 << 24) #define MX3_PWMCR_WAITEN (1 << 23) #define MX3_PWMCR_DBGEN (1 << 22) +#define MX3_PWMCR_CLKSRC_IPG_32K (3 << 16) #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) #define MX3_PWMCR_CLKSRC_IPG (1 << 16) #define MX3_PWMCR_EN (1 << 0) +#define MX3_SLOW_THRESHOLD_NS 100000 struct imx_chip { struct clk *clk_per; @@ -107,7 +109,13 @@ static int imx_pwm_config_v2(struct pwm_chip *chip, unsigned long period_cycles, duty_cycles, prescale; u32 cr; - c = clk_get_rate(imx->clk_per); + if (duty_ns > MX3_SLOW_THRESHOLD_NS) { + cr = MX3_PWMCR_CLKSRC_IPG_32K; + c = 32768; + } else { + cr = MX3_PWMCR_CLKSRC_IPG_HIGH; + c = clk_get_rate(imx->clk_per); + } c = c * period_ns; do_div(c, 1000000000); period_cycles = c; @@ -131,9 +139,9 @@ static int imx_pwm_config_v2(struct pwm_chip *chip, writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); writel(period_cycles, imx->mmio_base + MX3_PWMPR); - cr = MX3_PWMCR_PRESCALER(prescale) | + cr |= MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | - MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH; + MX3_PWMCR_DBGEN; if (test_bit(PWMF_ENABLED, &pwm->flags)) cr |= MX3_PWMCR_EN;