From patchwork Sat Jul 24 08:18:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 1509442 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=WRpX60z8; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GWzc76slPz9sXM for ; Sat, 24 Jul 2021 18:19:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234801AbhGXHia (ORCPT ); Sat, 24 Jul 2021 03:38:30 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:45906 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234774AbhGXHi3 (ORCPT ); Sat, 24 Jul 2021 03:38:29 -0400 X-UUID: b4fee2a433de458099db443222babec4-20210724 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=cXF42RrJw1ABsP86uX0FWJDg2YYpWsgUVihxQzX44zo=; b=WRpX60z83Hd7oe0+ZyomSLb7ofGc3HAUfzkG2SzzgEU8st9hHNVKbpkS6cEWeggmfRtDCQFVeMl4B2t/MdMDw8eXHB/LppWwjgxjyZ1mFnlflAk7ZjtakTj7OyHujjrR9ZpwPbc8Q2ZOA8IvtcYULJM5qv0sn9IdZQzg7HxdYwE=; X-UUID: b4fee2a433de458099db443222babec4-20210724 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2101701451; Sat, 24 Jul 2021 16:18:58 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 24 Jul 2021 16:18:51 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 24 Jul 2021 16:18:50 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v6 0/5] fix the clks on/off mismatch issue and switch pwm-mtk-disp to atomic APIs Date: Sat, 24 Jul 2021 16:18:44 +0800 Message-ID: <20210724081849.182108-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: 8631904548A5ADA78DF1745B7A3102CBCB1AF9C1E5A86DECAE8D376CF649AA202000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Changes since v5: - fix overflow. - Seperate the reg shadow as a single patch. Changes since v4: - Squash the commit "move the commit to clock enabled" to "adjust the clocks to avoid them mismatch". - Drop the useless comment about MT2701. - Reenable the clks "mm" and "main" in .enable(). - Fix typo. - Seperate get_state() operation as single patch. Changes since v3: - Seperate the clock sequence as single patch. - Fixup the reg commit when clocks sequence changed. - Merge the apply and get_state as single patch. Changes since v2: - Change commit messages to remove the clock operations for atomic APIs. - Rebase to v5.13 rc1. Changes since v1: - Seperate clock operation as single patch. - Seperate apply() as single patch. - Seperate get_state() operation as single patch. Jitao Shi (5): pwm: mtk-disp: adjust the clocks to avoid them mismatch pwm: mtk_disp: fix force reg to working reg. pwm: mtk_disp: implement atomic API .apply() pwm: mtk_disp: fix overflow in period and duty calcalation pwm: mtk_disp: implement atomic API .get_state() drivers/pwm/pwm-mtk-disp.c | 172 ++++++++++++++++++++----------------- 1 file changed, 92 insertions(+), 80 deletions(-)