diff mbox

[02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

Message ID 9ae7b152da13c094b024c54d27187aab96e439b3.1386752447.git.mohit.kumar@st.com
State Changes Requested
Headers show

Commit Message

Mohit KUMAR DCG Dec. 11, 2013, 9:38 a.m. UTC 
From: Pratyush Anand <pratyush.anand@st.com>

Move SPEAr1340 definitions to header files so that theese can be used by
other code too.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |   55 ++++++++++++++++++++++++++++++
 arch/arm/mach-spear/spear1340.c          |   54 -----------------------------
 2 files changed, 55 insertions(+), 54 deletions(-)

Comments

Arnd Bergmann Dec. 11, 2013, 10:48 p.m. UTC | #1 
On Wednesday 11 December 2013, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> Move SPEAr1340 definitions to header files so that theese can be used by
> other code too.

This looks like a regression, we intentionally made them private and they
should be moved into a proper driver instead of being globally visible.

> diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
> index 5cdc53d..4526f75 100644
> --- a/arch/arm/mach-spear/include/mach/spear.h
> +++ b/arch/arm/mach-spear/include/mach/spear.h
> @@ -86,6 +86,61 @@
>  /* Debug uart for linux, will be used for debug and uncompress messages */
>  #define SPEAR_DBG_UART_BASE			UART_BASE
>  
> +/* PCIe/SATA Base addresses */
> +#define SPEAR1340_SATA_BASE			UL(0xB1000000)
> +#define SPEAR1340_PCIE_BASE			UL(0xB1000000)

These should be in DT only.

> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
> +#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
> +#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
> +
> +#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
> +#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
> +#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)

The RST bits should probably go into a drivers/reset driver. Not sure what the
other registers do, but I'm sure we can find a driver for these too, possibly
they should be part of the PHY driver?

> @@ -22,60 +22,6 @@
>  #include <mach/spear.h>
>  
>  /* FIXME: Move SATA PHY code into a standalone driver */
> -
> -
> -/* PCIE - SATA configuration registers */
> -#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
> -	/* PCIE CFG MASks */
> -	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> -	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> -	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> -	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> -	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> -	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> -	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)

You leave the FIXME in place but move away the definitions it talks about.
Please fix the problem instead.

	Arnd
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Mohit KUMAR DCG Dec. 13, 2013, 4:18 a.m. UTC | #2 
Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Thursday, December 12, 2013 4:18 AM
> To: linux-arm-kernel@lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci@vger.kernel.org; Pratyush ANAND; spear-
> devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Move SPEAr1340 definitions to header files so that theese can be used
> > by other code too.
> 
> This looks like a regression, we intentionally made them private and they
> should be moved into a proper driver instead of being globally visible.
> 
> > diff --git a/arch/arm/mach-spear/include/mach/spear.h
> > b/arch/arm/mach-spear/include/mach/spear.h
> > index 5cdc53d..4526f75 100644
> > --- a/arch/arm/mach-spear/include/mach/spear.h
> > +++ b/arch/arm/mach-spear/include/mach/spear.h
> > @@ -86,6 +86,61 @@
> >  /* Debug uart for linux, will be used for debug and uncompress messages
> */
> >  #define SPEAR_DBG_UART_BASE			UART_BASE
> >
> > +/* PCIe/SATA Base addresses */
> > +#define SPEAR1340_SATA_BASE			UL(0xB1000000)
> > +#define SPEAR1340_PCIE_BASE			UL(0xB1000000)
> 
> These should be in DT only.
> 
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG			(VA_MISC_BASE +
> 0x100)
> > +#define SPEAR1340_PCM_WKUP_CFG
> 	(VA_MISC_BASE + 0x104)
> > +#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE +
> 0x108)
> > +
> > +#define SPEAR1340_PERIP1_SW_RST
> 	(VA_MISC_BASE + 0x318)
> > +#define SPEAR1340_PERIP2_SW_RST
> 	(VA_MISC_BASE + 0x31C)
> > +#define SPEAR1340_PERIP3_SW_RST
> 	(VA_MISC_BASE + 0x320)
> 	
> The RST bits should probably go into a drivers/reset driver. Not sure what the
> other registers do, but I'm sure we can find a driver for these too, possibly
> they should be part of the PHY driver?

-  Perhaps if we implement phy and reset driver then we may not require to move these definitions and
it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l 

Regards
Mohit
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Arnd Bergmann Dec. 14, 2013, 7:02 p.m. UTC | #3 
On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > The RST bits should probably go into a drivers/reset driver. Not sure what the
> > other registers do, but I'm sure we can find a driver for these too, possibly
> > they should be part of the PHY driver?
> 
> -  Perhaps if we implement phy and reset driver then we may not require to move these definitions and
> it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l 
> 

Ok, very good.

	Arnd
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Mohit KUMAR DCG Jan. 16, 2014, 7:25 a.m. UTC | #4 
Hi Arnd,


> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Sunday, December 15, 2013 12:33 AM
> To: Mohit KUMAR DCG
> Cc: linux-arm-kernel@lists.infradead.org; linux-pci@vger.kernel.org;
> Pratyush ANAND; spear-devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
> 
> On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > The RST bits should probably go into a drivers/reset driver. Not
> > > sure what the other registers do, but I'm sure we can find a driver
> > > for these too, possibly they should be part of the PHY driver?
> >
> > -  Perhaps if we implement phy and reset driver then we may not
> > require to move these definitions and it will address most of your
> > comments on SPEar13xx pcie driver. I am understanding and working on
> > this.l
> >

Though we are almost ready with v2. But few concerns:

There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.

We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
The same driver.

Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
Or we keep this new driver in arch/arm/mach-spear only.

Regards
Mohit

> 
> Ok, very good.
> 
> 	Arnd
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Pratyush ANAND Jan. 16, 2014, 9:19 a.m. UTC | #5 
On Thu, Jan 16, 2014 at 03:25:41PM +0800, Mohit KUMAR DCG wrote:
> Hi Arnd,
> 
> 
> > -----Original Message-----
> > From: Arnd Bergmann [mailto:arnd@arndb.de]
> > Sent: Sunday, December 15, 2013 12:33 AM
> > To: Mohit KUMAR DCG
> > Cc: linux-arm-kernel@lists.infradead.org; linux-pci@vger.kernel.org;
> > Pratyush ANAND; spear-devel; Viresh Kumar
> > Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> > header file
> > 
> > On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > > The RST bits should probably go into a drivers/reset driver. Not
> > > > sure what the other registers do, but I'm sure we can find a driver
> > > > for these too, possibly they should be part of the PHY driver?
> > >
> > > -  Perhaps if we implement phy and reset driver then we may not
> > > require to move these definitions and it will address most of your
> > > comments on SPEar13xx pcie driver. I am understanding and working on
> > > this.l
> > >
> 
> Though we are almost ready with v2. But few concerns:
> 
> There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> 
> We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> Node this driver's probe is called, which further adds ahci platform driver.
> We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> The same driver.
> 
> Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> Or we keep this new driver in arch/arm/mach-spear only.

I think this misc configuration register block resource should be
passed to syscon (drivers/mfd/syscon.c) driver.

regmap_update_bits should be used to update these registers and hence
to configure pcie/sata settings.

As far as place is concerned, that can be kept into mfd and can be
named as spear13xx-syscon.c

Whats your opinion arnd?

Regards
Pratyush

> 
> Regards
> Mohit
> 
> > 
> > Ok, very good.
> > 
> > 	Arnd
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Arnd Bergmann Jan. 16, 2014, 11:33 a.m. UTC | #6 
On Thursday 16 January 2014, Pratyush Anand wrote:
> > Though we are almost ready with v2. But few concerns:
> > 
> > There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> > registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> > For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> > 
> > We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> > Node this driver's probe is called, which further adds ahci platform driver.
> > We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> > The same driver.
> > 
> > Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> > Or we keep this new driver in arch/arm/mach-spear only.
> 
> I think this misc configuration register block resource should be
> passed to syscon (drivers/mfd/syscon.c) driver.
> 
> regmap_update_bits should be used to update these registers and hence
> to configure pcie/sata settings.
> 
> As far as place is concerned, that can be kept into mfd and can be
> named as spear13xx-syscon.c
> 
> Whats your opinion arnd?

That sounds exactly like what I would have suggested, thanks!

One question remains, which is what driver should directly use 
syscon_regmap_lookup_by_phandle() to get the syscon registers themselves,
and which ones should use a higher-level abstraction from spear13xx-syscon.c.

We can decide this on a case-by-case basis, but in general I would suggest
to have drivers use syscon_regmap_lookup_by_phandle directly as long as
it doesn't cause significant code duplication between drivers.

	Arnd
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Pratyush ANAND Jan. 16, 2014, 11:45 a.m. UTC | #7 
On Thu, Jan 16, 2014 at 07:33:40PM +0800, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Pratyush Anand wrote:
> > > Though we are almost ready with v2. But few concerns:
> > > 
> > > There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> > > registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> > > For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> > > 
> > > We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> > > Node this driver's probe is called, which further adds ahci platform driver.
> > > We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> > > The same driver.
> > > 
> > > Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> > > Or we keep this new driver in arch/arm/mach-spear only.
> > 
> > I think this misc configuration register block resource should be
> > passed to syscon (drivers/mfd/syscon.c) driver.
> > 
> > regmap_update_bits should be used to update these registers and hence
> > to configure pcie/sata settings.
> > 
> > As far as place is concerned, that can be kept into mfd and can be
> > named as spear13xx-syscon.c
> > 
> > Whats your opinion arnd?
> 
> That sounds exactly like what I would have suggested, thanks!
> 
> One question remains, which is what driver should directly use 
> syscon_regmap_lookup_by_phandle() to get the syscon registers themselves,
> and which ones should use a higher-level abstraction from spear13xx-syscon.c.
> 
> We can decide this on a case-by-case basis, but in general I would suggest
> to have drivers use syscon_regmap_lookup_by_phandle directly as long as
> it doesn't cause significant code duplication between drivers.

Yes, I think so.

Regards
Pratyush
> 
> 	Arnd
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diff mbox

Patch

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..4526f75 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -86,6 +86,61 @@ 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE			UART_BASE
 
+/* PCIe/SATA Base addresses */
+#define SPEAR1340_SATA_BASE			UL(0xB1000000)
+#define SPEAR1340_PCIE_BASE			UL(0xB1000000)
+
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
+#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
+#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
+
+#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
+#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
+#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
+			SPEAR1340_SATA_CFG_PM_CLK_EN | \
+			SPEAR1340_SATA_CFG_POWERUP_RESET | \
+			SPEAR1340_SATA_CFG_RX_CLK_EN | \
+			SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
+	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+
 #endif /* SPEAR13XX */
 
 #endif /* __MACH_SPEAR_H */
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..1b47609 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -22,60 +22,6 @@ 
 #include <mach/spear.h>
 
 /* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
 /* SATA device registration */
 static int sata_miphy_init(struct device *dev, void __iomem *addr)
 {