From patchwork Tue Feb 2 12:40:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Pimentel X-Patchwork-Id: 1434628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256 header.s=mail header.b=RZzkp0/o; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DVPhX0r4wz9sVt for ; Tue, 2 Feb 2021 23:46:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232022AbhBBMqc (ORCPT ); Tue, 2 Feb 2021 07:46:32 -0500 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:56128 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231761AbhBBMlz (ORCPT ); Tue, 2 Feb 2021 07:41:55 -0500 Received: from mailhost.synopsys.com (mdc-mailhost1.synopsys.com [10.225.0.209]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id D87FCC00BA; Tue, 2 Feb 2021 12:40:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1612269655; bh=rP7FcyZIb2UiEc7bBGnoSeIkNGnft9AjTq7ZKuTESmg=; h=From:To:Subject:Date:In-Reply-To:References:In-Reply-To: References:From; b=RZzkp0/o8ChPA+gazPHAPnCnh6phfhO/9/LOpmgSUtgUHkKCmI+5qWLUTpJmewBOD 9mjNzYQvJwvc1PYCQPmHHKTgXeDxkp2yVb3aM8kRsNrMAczugYABULckeMlGKgV8ku GAdh5dddLh5+C1DJNS9eGfqZk/zA3OfJfUzOogJBSRmDae5O4CXGhPvPKS7sSlgaWq fYOH7slpgfbK2q7gnaGTK5luUT9IeaHzJY0QpKugHyw7Z4r/MA6lrf0L1daUbqsdob Bf8D9Sb78rjOsQxAW9A7+3AJQbr2MwR4w4HDi5ps+WtO+1l7VCDVE+ExL/gqdNx1cc 8THdg/yci9LjQ== Received: from de02dwia024.internal.synopsys.com (de02dwia024.internal.synopsys.com [10.225.19.81]) by mailhost.synopsys.com (Postfix) with ESMTP id 9E9C6A0249; Tue, 2 Feb 2021 12:40:53 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Gustavo Pimentel To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Gustavo Pimentel , Dan Williams , Vinod Koul Subject: [PATCH v2 08/15] dmaengine: dw-edma: Reorder variables to keep consistency Date: Tue, 2 Feb 2021 13:40:22 +0100 Message-Id: <644f1e5d460a090c3c61ba8f9c776b0aef506a82.1612269537.git.gustavo.pimentel@synopsys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In the driver code structure, I tried to keep the code style consistency by writing the write channels instructions first, and then follow by the read channels instructions, mimicking the hardware implementation. However, this code style failed in some cases. This patch fixes that and no functional changes are expected. Signed-off-by: Gustavo Pimentel --- drivers/dma/dw-edma/dw-edma-pcie.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 7077d79..9e79eb5 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -20,8 +20,8 @@ #define DW_PCIE_VSEC_DMA_ID 0x6 #define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) -#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) #define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) +#define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) struct dw_edma_pcie_data { /* eDMA registers location */ @@ -39,8 +39,8 @@ struct dw_edma_pcie_data { /* Other */ enum dw_edma_map_format mf; u8 irqs; - u16 rd_ch_cnt; u16 wr_ch_cnt; + u16 rd_ch_cnt; }; static const struct dw_edma_pcie_data snps_edda_data = { @@ -59,8 +59,8 @@ static const struct dw_edma_pcie_data snps_edda_data = { /* Other */ .mf = EDMA_MF_EDMA_UNROLL, .irqs = 1, - .rd_ch_cnt = 0, .wr_ch_cnt = 0, + .rd_ch_cnt = 0, }; static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) @@ -99,8 +99,8 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev, pdata->rg_bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val); pci_read_config_dword(pdev, vsec + 0xc, &val); - pdata->rd_ch_cnt = FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val); pdata->wr_ch_cnt = FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val); + pdata->rd_ch_cnt = FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val); pci_read_config_dword(pdev, vsec + 0x14, &val); off = val; @@ -216,8 +216,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, dw->mf = vsec_data.mf; dw->nr_irqs = nr_irqs; dw->ops = &dw_edma_pcie_core_ops; - dw->rd_ch_cnt = vsec_data.rd_ch_cnt; dw->wr_ch_cnt = vsec_data.wr_ch_cnt; + dw->rd_ch_cnt = vsec_data.rd_ch_cnt; /* Debug info */ if (dw->mf == EDMA_MF_EDMA_LEGACY)