| Message ID | 45e6f7b2ab780e78b42490bb49e9a193a5598a07.1674468099.git.lukas@wunner.de |
|---|---|
| State | New |
| Headers | show |
| Series | Collection of DOE material | expand |
Lukas Wunner wrote: > The PCI core has just been amended to create a pci_doe_mb struct for > every DOE instance on device enumeration. > > Drop creation of a (duplicate) CDAT DOE mailbox on cxl probing in favor > of the one already created by the PCI core. > > Tested-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> > Signed-off-by: Lukas Wunner <lukas@wunner.de> > --- > drivers/cxl/core/pci.c | 27 +++++------------------ > drivers/cxl/cxlmem.h | 3 --- > drivers/cxl/pci.c | 49 ------------------------------------------ > 3 files changed, 5 insertions(+), 74 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index a02a2b005e6a..5cb6ffa8df0e 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -459,27 +459,6 @@ EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); > #define CXL_DOE_TABLE_ACCESS_LAST_ENTRY 0xffff > #define CXL_DOE_PROTOCOL_TABLE_ACCESS 2 > > -static struct pci_doe_mb *find_cdat_doe(struct device *uport) > -{ > - struct cxl_memdev *cxlmd; > - struct cxl_dev_state *cxlds; > - unsigned long index; > - void *entry; > - > - cxlmd = to_cxl_memdev(uport); > - cxlds = cxlmd->cxlds; > - > - xa_for_each(&cxlds->doe_mbs, index, entry) { > - struct pci_doe_mb *cur = entry; > - > - if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL, > - CXL_DOE_PROTOCOL_TABLE_ACCESS)) > - return cur; > - } > - > - return NULL; > -} > - > #define CDAT_DOE_REQ(entry_handle) \ > (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \ > CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \ > @@ -569,10 +548,14 @@ void read_cdat_data(struct cxl_port *port) > struct pci_doe_mb *cdat_doe; > struct device *dev = &port->dev; > struct device *uport = port->uport; > + struct cxl_memdev *cxlmd = to_cxl_memdev(uport); > + struct cxl_dev_state *cxlds = cxlmd->cxlds; > + struct pci_dev *pdev = to_pci_dev(cxlds->dev); > size_t cdat_length; > int rc; > > - cdat_doe = find_cdat_doe(uport); > + cdat_doe = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL, > + CXL_DOE_PROTOCOL_TABLE_ACCESS); > if (!cdat_doe) { > dev_dbg(dev, "No CDAT mailbox\n"); > return; > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index ab138004f644..e1a1b23cf56c 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -227,7 +227,6 @@ struct cxl_endpoint_dvsec_info { > * @component_reg_phys: register base of component registers > * @info: Cached DVSEC information about the device. > * @serial: PCIe Device Serial Number > - * @doe_mbs: PCI DOE mailbox array > * @mbox_send: @dev specific transport for transmitting mailbox commands > * > * See section 8.2.9.5.2 Capacity Configuration and Label Storage for > @@ -264,8 +263,6 @@ struct cxl_dev_state { > resource_size_t component_reg_phys; > u64 serial; > > - struct xarray doe_mbs; > - > int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); > }; > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 33083a522fd1..f8b8e514a3c6 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -8,7 +8,6 @@ > #include <linux/mutex.h> > #include <linux/list.h> > #include <linux/pci.h> > -#include <linux/pci-doe.h> > #include <linux/aer.h> > #include <linux/io.h> > #include "cxlmem.h" > @@ -359,52 +358,6 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > return rc; > } > > -static void cxl_pci_destroy_doe(void *mbs) > -{ > - xa_destroy(mbs); > -} > - > -static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > -{ > - struct device *dev = cxlds->dev; > - struct pci_dev *pdev = to_pci_dev(dev); > - u16 off = 0; > - > - xa_init(&cxlds->doe_mbs); > - if (devm_add_action(&pdev->dev, cxl_pci_destroy_doe, &cxlds->doe_mbs)) { > - dev_err(dev, "Failed to create XArray for DOE's\n"); > - return; > - } > - > - /* > - * Mailbox creation is best effort. Higher layers must determine if > - * the lack of a mailbox for their protocol is a device failure or not. > - */ > - pci_doe_for_each_off(pdev, off) { > - struct pci_doe_mb *doe_mb; > - > - doe_mb = pcim_doe_create_mb(pdev, off); > - if (IS_ERR(doe_mb)) { > - dev_err(dev, "Failed to create MB object for MB @ %x\n", > - off); > - continue; > - } > - > - if (!pci_request_config_region_exclusive(pdev, off, > - PCI_DOE_CAP_SIZEOF, > - dev_name(dev))) > - pci_err(pdev, "Failed to exclude DOE registers\n"); > - > - if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) { > - dev_err(dev, "xa_insert failed to insert MB @ %x\n", > - off); > - continue; > - } > - > - dev_dbg(dev, "Created DOE mailbox @%x\n", off); > - } > -} > - > /* > * Assume that any RCIEP that emits the CXL memory expander class code > * is an RCD > @@ -469,8 +422,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > > cxlds->component_reg_phys = map.resource; > > - devm_cxl_pci_create_doe(cxlds); > - > rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component, > &map, BIT(CXL_CM_CAP_CAP_ID_RAS)); > if (rc) > -- > 2.39.1 >
On Mon, 23 Jan 2023 11:18:00 +0100 Lukas Wunner <lukas@wunner.de> wrote: > The PCI core has just been amended to create a pci_doe_mb struct for > every DOE instance on device enumeration. > > Drop creation of a (duplicate) CDAT DOE mailbox on cxl probing in favor > of the one already created by the PCI core. > > Tested-by: Ira Weiny <ira.weiny@intel.com> > Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a02a2b005e6a..5cb6ffa8df0e 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -459,27 +459,6 @@ EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); #define CXL_DOE_TABLE_ACCESS_LAST_ENTRY 0xffff #define CXL_DOE_PROTOCOL_TABLE_ACCESS 2 -static struct pci_doe_mb *find_cdat_doe(struct device *uport) -{ - struct cxl_memdev *cxlmd; - struct cxl_dev_state *cxlds; - unsigned long index; - void *entry; - - cxlmd = to_cxl_memdev(uport); - cxlds = cxlmd->cxlds; - - xa_for_each(&cxlds->doe_mbs, index, entry) { - struct pci_doe_mb *cur = entry; - - if (pci_doe_supports_prot(cur, PCI_DVSEC_VENDOR_ID_CXL, - CXL_DOE_PROTOCOL_TABLE_ACCESS)) - return cur; - } - - return NULL; -} - #define CDAT_DOE_REQ(entry_handle) \ (FIELD_PREP(CXL_DOE_TABLE_ACCESS_REQ_CODE, \ CXL_DOE_TABLE_ACCESS_REQ_CODE_READ) | \ @@ -569,10 +548,14 @@ void read_cdat_data(struct cxl_port *port) struct pci_doe_mb *cdat_doe; struct device *dev = &port->dev; struct device *uport = port->uport; + struct cxl_memdev *cxlmd = to_cxl_memdev(uport); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct pci_dev *pdev = to_pci_dev(cxlds->dev); size_t cdat_length; int rc; - cdat_doe = find_cdat_doe(uport); + cdat_doe = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL, + CXL_DOE_PROTOCOL_TABLE_ACCESS); if (!cdat_doe) { dev_dbg(dev, "No CDAT mailbox\n"); return; diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index ab138004f644..e1a1b23cf56c 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -227,7 +227,6 @@ struct cxl_endpoint_dvsec_info { * @component_reg_phys: register base of component registers * @info: Cached DVSEC information about the device. * @serial: PCIe Device Serial Number - * @doe_mbs: PCI DOE mailbox array * @mbox_send: @dev specific transport for transmitting mailbox commands * * See section 8.2.9.5.2 Capacity Configuration and Label Storage for @@ -264,8 +263,6 @@ struct cxl_dev_state { resource_size_t component_reg_phys; u64 serial; - struct xarray doe_mbs; - int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); }; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 33083a522fd1..f8b8e514a3c6 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -8,7 +8,6 @@ #include <linux/mutex.h> #include <linux/list.h> #include <linux/pci.h> -#include <linux/pci-doe.h> #include <linux/aer.h> #include <linux/io.h> #include "cxlmem.h" @@ -359,52 +358,6 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, return rc; } -static void cxl_pci_destroy_doe(void *mbs) -{ - xa_destroy(mbs); -} - -static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) -{ - struct device *dev = cxlds->dev; - struct pci_dev *pdev = to_pci_dev(dev); - u16 off = 0; - - xa_init(&cxlds->doe_mbs); - if (devm_add_action(&pdev->dev, cxl_pci_destroy_doe, &cxlds->doe_mbs)) { - dev_err(dev, "Failed to create XArray for DOE's\n"); - return; - } - - /* - * Mailbox creation is best effort. Higher layers must determine if - * the lack of a mailbox for their protocol is a device failure or not. - */ - pci_doe_for_each_off(pdev, off) { - struct pci_doe_mb *doe_mb; - - doe_mb = pcim_doe_create_mb(pdev, off); - if (IS_ERR(doe_mb)) { - dev_err(dev, "Failed to create MB object for MB @ %x\n", - off); - continue; - } - - if (!pci_request_config_region_exclusive(pdev, off, - PCI_DOE_CAP_SIZEOF, - dev_name(dev))) - pci_err(pdev, "Failed to exclude DOE registers\n"); - - if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) { - dev_err(dev, "xa_insert failed to insert MB @ %x\n", - off); - continue; - } - - dev_dbg(dev, "Created DOE mailbox @%x\n", off); - } -} - /* * Assume that any RCIEP that emits the CXL memory expander class code * is an RCD @@ -469,8 +422,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) cxlds->component_reg_phys = map.resource; - devm_cxl_pci_create_doe(cxlds); - rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component, &map, BIT(CXL_CM_CAP_CAP_ID_RAS)); if (rc)