| Message ID | 20261001092227.3004747-9-smadhavan@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI/CXL: Add CXL reset support for Type 2 devices | expand |
> An HDM decoder with a nonzero size can report a base and size whose end > address wraps the 64-bit address space. Reject that programming before > publishing the decoder range, so enumeration and later reset handling > cannot use the wrapped range. > > Use check_add_overflow() for nonzero ranges. Preserve the existing > empty-range representation for zero-size decoders. > > Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com> Sashiko has reviewed this patch and found no issues. It looks great!
On 10/1/26 2:22 AM, Srirangan Madhavan wrote: > An HDM decoder with a nonzero size can report a base and size whose end > address wraps the 64-bit address space. Reject that programming before > publishing the decoder range, so enumeration and later reset handling > cannot use the wrapped range. > > Use check_add_overflow() for nonzero ranges. Preserve the existing > empty-range representation for zero-size decoders. Why split this out instead of just introduce it when the function is introduced in the previous patch? DJ > > Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com> > --- > drivers/cxl/core/resource.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c > index 8dfeb12de8c9..8d2fbc49a06f 100644 > --- a/drivers/cxl/core/resource.c > +++ b/drivers/cxl/core/resource.c > @@ -115,16 +115,21 @@ int cxl_hdm_unpack_decoder(struct cxl_decoder_settings *settings, int id, > int interleave_ways; > unsigned long flags = 0; > struct range hpa_range; > + u64 end; > int rc; > > if (!committed) > size = 0; > if (base == U64_MAX || size == U64_MAX) > return -ENXIO; > + if (size && check_add_overflow(base, size - 1, &end)) > + return -ENXIO; > + if (!size) > + end = base - 1; > > hpa_range = (struct range) { > .start = base, > - .end = base + size - 1, > + .end = end, > }; > > if (committed) {
diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c index 8dfeb12de8c9..8d2fbc49a06f 100644 --- a/drivers/cxl/core/resource.c +++ b/drivers/cxl/core/resource.c @@ -115,16 +115,21 @@ int cxl_hdm_unpack_decoder(struct cxl_decoder_settings *settings, int id, int interleave_ways; unsigned long flags = 0; struct range hpa_range; + u64 end; int rc; if (!committed) size = 0; if (base == U64_MAX || size == U64_MAX) return -ENXIO; + if (size && check_add_overflow(base, size - 1, &end)) + return -ENXIO; + if (!size) + end = base - 1; hpa_range = (struct range) { .start = base, - .end = base + size - 1, + .end = end, }; if (committed) {
An HDM decoder with a nonzero size can report a base and size whose end address wraps the 64-bit address space. Reject that programming before publishing the decoder range, so enumeration and later reset handling cannot use the wrapped range. Use check_add_overflow() for nonzero ranges. Preserve the existing empty-range representation for zero-size decoders. Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com> --- drivers/cxl/core/resource.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)