| Message ID | 20260901-pci-tc9563-aux-v1-1-dd9b80738e70@oss.qualcomm.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI/pwrctrl: tc9563: introduce support for embedded GPIO controller | expand |
On Tue, Sep 01, 2026 at 12:27:53PM +0200, Lorenzo Bianconi wrote: > The TC9563 PCIe switch embeds a GPIO controller providing 37 GPIO > lines. The controller is not bound by a device tree compatible string > but is registered as an auxiliary device by the TC9563 power controller > and accessed through the same register map, so the GPIO node has no > compatible of its own. > > Describe the embedded GPIO controller as a "gpio" child node of the > switch, document the per-port reset-gpios property, and update the > example to reference the controller from the downstream port reset > lines. > > Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com> > --- > .../devicetree/bindings/pci/toshiba,tc9563.yaml | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml > index f084830c6d0c..47cd58c14e4a 100644 > --- a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml > +++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml > @@ -54,6 +54,23 @@ properties: > - description: I2C slave address > > patternProperties: > + "^gpio(@[0-9a-f]+)?$": Why the unit address is optional? And what does it even represent? > + description: > + child node describing the embedded GPIO controller available in TC9563 No, this is a PCIe switch so the children are PCI bridges. This does not fit at all. I do not understand why this node was created in the first place - what device does it represent? > + PCIe switch. The controller is registered as an auxiliary device by the > + TC9563 power controller and accessed through the i2c device. > + type: object > + additionalProperties: false > + properties: And why there is no reg here? > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 Are you sure you are not re-implementing https://lore.kernel.org/all/20260701-shikra-upstream-v1-3-e1a721eb8943@oss.qualcomm.com/ ? > + > + required: > + - gpio-controller > + - "#gpio-cells" > + > "^pcie@[1-2],0$": > description: > child nodes describing the internal downstream ports of > @@ -62,6 +79,11 @@ patternProperties: > allOf: > - $ref: "#/$defs/tc9563-node" > - $ref: /schemas/pci/pci-pci-bridge.yaml# > + properties: > + reset-gpios: > + maxItems: 1 > + description: > + GPIO controlling the PERST# reset of the downstream port. > unevaluatedProperties: false > > "^pcie@[3],0$": > @@ -149,6 +171,11 @@ examples: > > resx-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; > > + tc9563_gpio: gpio { > + gpio-controller; > + #gpio-cells = <2>; Where are any resources? Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml index f084830c6d0c..47cd58c14e4a 100644 --- a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml +++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml @@ -54,6 +54,23 @@ properties: - description: I2C slave address patternProperties: + "^gpio(@[0-9a-f]+)?$": + description: + child node describing the embedded GPIO controller available in TC9563 + PCIe switch. The controller is registered as an auxiliary device by the + TC9563 power controller and accessed through the i2c device. + type: object + additionalProperties: false + properties: + gpio-controller: true + + "#gpio-cells": + const: 2 + + required: + - gpio-controller + - "#gpio-cells" + "^pcie@[1-2],0$": description: child nodes describing the internal downstream ports of @@ -62,6 +79,11 @@ patternProperties: allOf: - $ref: "#/$defs/tc9563-node" - $ref: /schemas/pci/pci-pci-bridge.yaml# + properties: + reset-gpios: + maxItems: 1 + description: + GPIO controlling the PERST# reset of the downstream port. unevaluatedProperties: false "^pcie@[3],0$": @@ -149,6 +171,11 @@ examples: resx-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + tc9563_gpio: gpio { + gpio-controller; + #gpio-cells = <2>; + }; + pcie@1,0 { compatible = "pciclass,0604"; reg = <0x20800 0x0 0x0 0x0 0x0>; @@ -158,6 +185,8 @@ examples: ranges; bus-range = <0x03 0xff>; + reset-gpios = <&tc9563_gpio 2 GPIO_ACTIVE_LOW>; + toshiba,no-dfe-support; }; @@ -170,6 +199,8 @@ examples: ranges; bus-range = <0x04 0xff>; + reset-gpios = <&tc9563_gpio 3 GPIO_ACTIVE_LOW>; + toshiba,tx-amplitude-microvolt = <10>; };
The TC9563 PCIe switch embeds a GPIO controller providing 37 GPIO lines. The controller is not bound by a device tree compatible string but is registered as an auxiliary device by the TC9563 power controller and accessed through the same register map, so the GPIO node has no compatible of its own. Describe the embedded GPIO controller as a "gpio" child node of the switch, document the per-port reset-gpios property, and update the example to reference the controller from the downstream port reset lines. Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com> --- .../devicetree/bindings/pci/toshiba,tc9563.yaml | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+)