@@ -75,6 +75,10 @@ resource_size_t __rcrb_to_component(struct device *dev,
enum cxl_rcrb which);
u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
+#define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0)
+#define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0)
+#define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8)
+
extern struct rw_semaphore cxl_dpa_rwsem;
extern struct rw_semaphore cxl_region_rwsem;
@@ -514,6 +514,8 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri
u32 bar0, bar1;
u16 cmd;
u32 id;
+ u16 offset;
+ u32 cap_hdr;
if (which == CXL_RCRB_UPSTREAM)
rcrb += SZ_4K;
@@ -537,6 +539,20 @@ resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri
cmd = readw(addr + PCI_COMMAND);
bar0 = readl(addr + PCI_BASE_ADDRESS_0);
bar1 = readl(addr + PCI_BASE_ADDRESS_1);
+ offset = FIELD_GET(PCI_RCRB_CAP_LIST_ID_MASK, readw(addr + PCI_CAPABILITY_LIST));
+ cap_hdr = readl(addr + offset);
+ while ((FIELD_GET(PCI_RCRB_CAP_HDR_ID_MASK, cap_hdr)) != PCI_CAP_ID_EXP) {
+ offset = FIELD_GET(PCI_RCRB_CAP_HDR_NEXT_MASK, cap_hdr);
+ if (offset == 0 || offset > SZ_4K)
+ break;
+ cap_hdr = readl(addr + offset);
+ }
+ if (offset) {
+ ri->rcd_lnkcap = readl(addr + offset + PCI_EXP_LNKCAP);
+ ri->rcd_lnkctrl = readl(addr + offset + PCI_EXP_LNKCTL);
+ ri->rcd_lnkstatus = readl(addr + offset + PCI_EXP_LNKSTA);
+ }
+
iounmap(addr);
release_mem_region(rcrb, SZ_4K);
@@ -646,6 +646,9 @@ cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
struct cxl_rcrb_info {
resource_size_t base;
+ u16 rcd_lnkstatus;
+ u16 rcd_lnkctrl;
+ u32 rcd_lnkcap;
u16 aer_cap;
};