| Message ID | 20240506161510.2841755-2-sean.anderson@linux.dev |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: xilinx-nwl: Add phy support | expand |
On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote: > Add phys properties so Linux can power-on/configure the GTR > transcievers. > > Signed-off-by: Sean Anderson <sean.anderson@linux.dev> > --- > > Changes in v2: > - Remove phy-names > - Add an example > > Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > index 426f90a47f35..693b29039a9b 100644 > --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > @@ -61,6 +61,10 @@ properties: > interrupt-map: > maxItems: 4 > > + phys: > + minItems: 1 > + maxItems: 4 I assume this is 1 phy per lane, but don't make me assume and define it. Rob
On 5/7/24 16:06, Rob Herring wrote: > On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote: >> Add phys properties so Linux can power-on/configure the GTR >> transcievers. >> >> Signed-off-by: Sean Anderson <sean.anderson@linux.dev> >> --- >> >> Changes in v2: >> - Remove phy-names >> - Add an example >> >> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> index 426f90a47f35..693b29039a9b 100644 >> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >> @@ -61,6 +61,10 @@ properties: >> interrupt-map: >> maxItems: 4 >> >> + phys: >> + minItems: 1 >> + maxItems: 4 > > I assume this is 1 phy per lane, but don't make me assume and define it. > > Rob It's one per lane. I'll add that to the description. --Sean
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 426f90a47f35..693b29039a9b 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -61,6 +61,10 @@ properties: interrupt-map: maxItems: 4 + phys: + minItems: 1 + maxItems: 4 + power-domains: maxItems: 1 @@ -110,6 +114,7 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/phy/phy.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> soc { #address-cells = <2>; @@ -138,6 +143,7 @@ examples: <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; msi-parent = <&nwl_pcie>; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; power-domains = <&zynqmp_firmware PD_PCIE>; iommus = <&smmu 0x4d0>; pcie_intc: legacy-interrupt-controller {
Add phys properties so Linux can power-on/configure the GTR transcievers. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> --- Changes in v2: - Remove phy-names - Add an example Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++ 1 file changed, 6 insertions(+)