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29 Apr 2024 03:47:38 -0700 X-CSE-ConnectionGUID: TIoj9xeOS469TRfuYgY/TQ== X-CSE-MsgGUID: gWr1b7dpS1ObYa3kQl/YNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896766" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:35 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Linus Walleij , Lorenzo Pieralisi , linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 06/10] PCI: ixp4xx: Replace 1 with PCI_CONF1_TRANSACTION Date: Mon, 29 Apr 2024 13:46:29 +0300 Message-Id: <20240429104633.11060-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add PCI_CONF1_TRANSACTION and replace literal 1 within PCI Configuration Space Type 1 address with it. Signed-off-by: Ilpo Järvinen Reviewed-by: Linus Walleij --- drivers/pci/controller/pci-ixp4xx.c | 2 +- include/linux/pci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/pci-ixp4xx.c index 44639838df9c..ec0125344ca1 100644 --- a/drivers/pci/controller/pci-ixp4xx.c +++ b/drivers/pci/controller/pci-ixp4xx.c @@ -194,7 +194,7 @@ static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) /* type 1 */ return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), where) & - ~PCI_CONF1_ENABLE) | 1; + ~PCI_CONF1_ENABLE) | PCI_CONF1_TRANSACTION; } } diff --git a/include/linux/pci.h b/include/linux/pci.h index 4c4e3bb52a0a..df613428bc4d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1191,6 +1191,7 @@ void pci_sort_breadthfirst(void); * See PCI Local Bus Specification, Revision 3.0, * Section 3.2.2.3.2, Figure 3-1 and 3-2, p. 48-50. */ +#define PCI_CONF1_TRANSACTION BIT(0) #define PCI_CONF_REG 0x000000ffU /* common for Type 0/1 */ #define PCI_CONF_FUNC 0x00000700U /* common for Type 0/1 */ #define PCI_CONF1_DEV 0x0000f800U