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29 Apr 2024 03:48:08 -0700 X-CSE-ConnectionGUID: bOPtYgLLRmirNCTAizYk1Q== X-CSE-MsgGUID: 0IPQ+Z+tQTiB4Q/+A6EYGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896807" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:48:04 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 09/10] PCI: mvebu: Use generic PCI Conf Type 1 helper Date: Mon, 29 Apr 2024 13:46:32 +0300 Message-Id: <20240429104633.11060-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert mvebu to use the pci_conf1_ext_addr() helper from PCI core to calculate PCI Configuration Space address for Type 1 access. Signed-off-by: Ilpo Järvinen Tested-by: Andrew Lunn --- drivers/pci/controller/pci-mvebu.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 29fe09c99e7d..1908754ee6fd 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -45,15 +45,6 @@ #define PCIE_WIN5_BASE_OFF 0x1884 #define PCIE_WIN5_REMAP_OFF 0x188c #define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN 0x80000000 -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) -#define PCIE_CONF_ADDR(bus, devfn, where) \ - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ - PCIE_CONF_ADDR_EN) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_INT_CAUSE_OFF 0x1900 #define PCIE_INT_UNMASK_OFF 0x1910 @@ -361,7 +352,7 @@ static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, conf_data = port->base + PCIE_CONF_DATA_OFF; - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + mvebu_writel(port, pci_conf1_ext_addr(bus->number, devfn, where, true), PCIE_CONF_ADDR_OFF); switch (size) { @@ -397,7 +388,7 @@ static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, conf_data = port->base + PCIE_CONF_DATA_OFF; - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + mvebu_writel(port, pci_conf1_ext_addr(bus->number, devfn, where, true), PCIE_CONF_ADDR_OFF); switch (size) {