| Message ID | 20240314-pci-epf-rework-v1-10-6134e6c1d491@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: endpoint: Make host reboot handling more robust | expand |
On Thu, Mar 14, 2024 at 08:53:49PM +0530, Manivannan Sadhasivam wrote: > DWC specific start_link() and stop_link() callbacks are supposed to start > and stop the link training of the PCIe bus. But the current implementation > of this driver enables/disables the PERST# IRQ. > > Even though this is not causing any issues, this creates inconsistency > among the controller drivers. So for the sake of consistency, let's just > start/stop the link training in these callbacks. > > Also, PERST# IRQ is now enabled from the start itself, thus allowing the > controller driver to initialize the registers when PERST# gets deasserted > without waiting for the user intervention though configfs. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Nice change: Reviewed-by: Niklas Cassel <cassel@kernel.org> If you dump LTSSM after a PERST assert + deassert, using e.g. dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); to dump the debug registers (see dw_pcie_link_up()) do you see that PCIE_PORT_DEBUG1_LINK_IN_TRAINING is set? I was thinking that perhaps there was a thought behind this original design, that you had to explicitly set LTSSM_EN after a fundamental core reset, because it would get cleared? (It it is implemented like signals and not registers, then this change should be fine.) Kind regards, Niklas > drivers/pci/controller/dwc/pcie-qcom-ep.c | 21 +++++++++++++-------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index 811f250e967a..653e4ace0a07 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -122,6 +122,9 @@ > /* PARF_CFG_BITS register fields */ > #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) > > +/* PARF_LTSSM register fields */ > +#define LTSSM_EN BIT(8) > + > /* ELBI registers */ > #define ELBI_SYS_STTS 0x08 > #define ELBI_CS2_ENABLE 0xa4 > @@ -250,8 +253,12 @@ static int qcom_pcie_dw_link_up(struct dw_pcie *pci) > static int qcom_pcie_dw_start_link(struct dw_pcie *pci) > { > struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); > + u32 val; > > - enable_irq(pcie_ep->perst_irq); > + /* Enable LTSSM */ > + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); > + val |= LTSSM_EN; > + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > > return 0; > } > @@ -259,8 +266,12 @@ static int qcom_pcie_dw_start_link(struct dw_pcie *pci) > static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) > { > struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); > + u32 val; > > - disable_irq(pcie_ep->perst_irq); > + /* Disable LTSSM */ > + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); > + val &= ~LTSSM_EN; > + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > } > > static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, > @@ -484,11 +495,6 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) > > dw_pcie_ep_init_notify(&pcie_ep->pci.ep); > > - /* Enable LTSSM */ > - val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); > - val |= BIT(8); > - writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > - > return 0; > > err_disable_resources: > @@ -707,7 +713,6 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, > } > > pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); > - irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); > ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, > qcom_pcie_ep_perst_irq_thread, > IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > > -- > 2.25.1 >
On Fri, Mar 22, 2024 at 05:10:54PM +0100, Niklas Cassel wrote: > On Thu, Mar 14, 2024 at 08:53:49PM +0530, Manivannan Sadhasivam wrote: > > DWC specific start_link() and stop_link() callbacks are supposed to start > > and stop the link training of the PCIe bus. But the current implementation > > of this driver enables/disables the PERST# IRQ. > > > > Even though this is not causing any issues, this creates inconsistency > > among the controller drivers. So for the sake of consistency, let's just > > start/stop the link training in these callbacks. > > > > Also, PERST# IRQ is now enabled from the start itself, thus allowing the > > controller driver to initialize the registers when PERST# gets deasserted > > without waiting for the user intervention though configfs. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > Nice change: > Reviewed-by: Niklas Cassel <cassel@kernel.org> > > If you dump LTSSM after a PERST assert + deassert, > using e.g. dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); > to dump the debug registers (see dw_pcie_link_up()) > do you see that PCIE_PORT_DEBUG1_LINK_IN_TRAINING is set? > > I was thinking that perhaps there was a thought behind > this original design, that you had to explicitly set > LTSSM_EN after a fundamental core reset, because it > would get cleared? > Well, you are right. I was hoping to get an answer from Kishon/Vidya, but you throwed the light. I will drop these 2 patches. Thanks! - Mani > (It it is implemented like signals and not registers, > then this change should be fine.) > > > Kind regards, > Niklas > > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 21 +++++++++++++-------- > > 1 file changed, 13 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > > index 811f250e967a..653e4ace0a07 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > > @@ -122,6 +122,9 @@ > > /* PARF_CFG_BITS register fields */ > > #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) > > > > +/* PARF_LTSSM register fields */ > > +#define LTSSM_EN BIT(8) > > + > > /* ELBI registers */ > > #define ELBI_SYS_STTS 0x08 > > #define ELBI_CS2_ENABLE 0xa4 > > @@ -250,8 +253,12 @@ static int qcom_pcie_dw_link_up(struct dw_pcie *pci) > > static int qcom_pcie_dw_start_link(struct dw_pcie *pci) > > { > > struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); > > + u32 val; > > > > - enable_irq(pcie_ep->perst_irq); > > + /* Enable LTSSM */ > > + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); > > + val |= LTSSM_EN; > > + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > > > > return 0; > > } > > @@ -259,8 +266,12 @@ static int qcom_pcie_dw_start_link(struct dw_pcie *pci) > > static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) > > { > > struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); > > + u32 val; > > > > - disable_irq(pcie_ep->perst_irq); > > + /* Disable LTSSM */ > > + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); > > + val &= ~LTSSM_EN; > > + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > > } > > > > static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, > > @@ -484,11 +495,6 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) > > > > dw_pcie_ep_init_notify(&pcie_ep->pci.ep); > > > > - /* Enable LTSSM */ > > - val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); > > - val |= BIT(8); > > - writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); > > - > > return 0; > > > > err_disable_resources: > > @@ -707,7 +713,6 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, > > } > > > > pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); > > - irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); > > ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, > > qcom_pcie_ep_perst_irq_thread, > > IRQF_TRIGGER_HIGH | IRQF_ONESHOT, > > > > -- > > 2.25.1 > > >
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 811f250e967a..653e4ace0a07 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -122,6 +122,9 @@ /* PARF_CFG_BITS register fields */ #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1) +/* PARF_LTSSM register fields */ +#define LTSSM_EN BIT(8) + /* ELBI registers */ #define ELBI_SYS_STTS 0x08 #define ELBI_CS2_ENABLE 0xa4 @@ -250,8 +253,12 @@ static int qcom_pcie_dw_link_up(struct dw_pcie *pci) static int qcom_pcie_dw_start_link(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + u32 val; - enable_irq(pcie_ep->perst_irq); + /* Enable LTSSM */ + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); + val |= LTSSM_EN; + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); return 0; } @@ -259,8 +266,12 @@ static int qcom_pcie_dw_start_link(struct dw_pcie *pci) static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) { struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + u32 val; - disable_irq(pcie_ep->perst_irq); + /* Disable LTSSM */ + val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); + val &= ~LTSSM_EN; + writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); } static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base, @@ -484,11 +495,6 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) dw_pcie_ep_init_notify(&pcie_ep->pci.ep); - /* Enable LTSSM */ - val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); - val |= BIT(8); - writel_relaxed(val, pcie_ep->parf + PARF_LTSSM); - return 0; err_disable_resources: @@ -707,7 +713,6 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, } pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); - irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
DWC specific start_link() and stop_link() callbacks are supposed to start and stop the link training of the PCIe bus. But the current implementation of this driver enables/disables the PERST# IRQ. Even though this is not causing any issues, this creates inconsistency among the controller drivers. So for the sake of consistency, let's just start/stop the link training in these callbacks. Also, PERST# IRQ is now enabled from the start itself, thus allowing the controller driver to initialize the registers when PERST# gets deasserted without waiting for the user intervention though configfs. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-)