diff mbox series

[v3,8/9] PCI: rockchip-ep: Set a 64-bit BAR if requested

Message ID 20240313105804.100168-9-cassel@kernel.org
State New
Headers show
Series PCI: endpoint: set prefetchable bit for 64-bit BARs | expand

Commit Message

Niklas Cassel March 13, 2024, 10:58 a.m. UTC 
Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB
is invalid if 64-bit flag is not set") it has been impossible to get the
.set_bar() callback with a BAR size > 4 GB, if the BAR was also not
requested to be configured as a 64-bit BAR.

It is however possible that an EPF driver configures a BAR as 64-bit,
even if the requested size is < 4 GB.

Respect the requested BAR configuration, just like how it is already
repected with regards to the prefetchable bit.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Manivannan Sadhasivam March 15, 2024, 5:47 a.m. UTC | #1 
On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB
> is invalid if 64-bit flag is not set") it has been impossible to get the
> .set_bar() callback with a BAR size > 4 GB, if the BAR was also not
> requested to be configured as a 64-bit BAR.
> 
> It is however possible that an EPF driver configures a BAR as 64-bit,
> even if the requested size is < 4 GB.

2 GB

> 
> Respect the requested BAR configuration, just like how it is already
> repected with regards to the prefetchable bit.
> 
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Ah, I missed this one. But the same comment as previous one applies to this
patch also.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>  drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> index c9046e97a1d2..57472cf48997 100644
> --- a/drivers/pci/controller/pcie-rockchip-ep.c
> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
>  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
>  	} else {
>  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> -		bool is_64bits = sz > SZ_2G;
> +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
>  
>  		if (is_64bits && (bar & 1))
>  			return -EINVAL;
> -- 
> 2.44.0
>
Bjorn Helgaas April 12, 2024, 5:51 p.m. UTC | #2 
On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB
> is invalid if 64-bit flag is not set") it has been impossible to get the
> .set_bar() callback with a BAR size > 4 GB, if the BAR was also not
> requested to be configured as a 64-bit BAR.
> 
> It is however possible that an EPF driver configures a BAR as 64-bit,
> even if the requested size is < 4 GB.
> 
> Respect the requested BAR configuration, just like how it is already
> repected with regards to the prefetchable bit.

Does this (and the similar cadence patch) need a Fixes: tag for
f25b5fae29d4?

> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> index c9046e97a1d2..57472cf48997 100644
> --- a/drivers/pci/controller/pcie-rockchip-ep.c
> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
>  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
>  	} else {
>  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> -		bool is_64bits = sz > SZ_2G;
> +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
>  
>  		if (is_64bits && (bar & 1))
>  			return -EINVAL;
> -- 
> 2.44.0
>
Bjorn Helgaas April 12, 2024, 6:59 p.m. UTC | #3 
On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> ...

> --- a/drivers/pci/controller/pcie-rockchip-ep.c
> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
>  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
>  	} else {
>  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> -		bool is_64bits = sz > SZ_2G;
> +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
>  
>  		if (is_64bits && (bar & 1))
>  			return -EINVAL;

Completely unrelated to *these* patches, but the BAR_CFG_CTRL
definitions in both cadence and rockchip lead to some awkward case
analysis:

  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS              0x4
  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS     0x5
  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS              0x6
  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS     0x7

  if (is_64bits && is_prefetch)
          ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
  else if (is_prefetch)
          ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
  else if (is_64bits)
          ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
  else
          ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;

that *could* be just something like this:

  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM           0x4
  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_64BITS        0x2
  #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH      0x1

  ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM;
  if (is_64bits)
    ctrl |= ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_64BITS;
  if (is_prefetch)
    ctrl |= ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH;
Niklas Cassel April 12, 2024, 9:39 p.m. UTC | #4 
On Fri, Apr 12, 2024 at 12:51:27PM -0500, Bjorn Helgaas wrote:
> On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> > Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB
> > is invalid if 64-bit flag is not set") it has been impossible to get the
> > .set_bar() callback with a BAR size > 4 GB, if the BAR was also not
> > requested to be configured as a 64-bit BAR.
> > 
> > It is however possible that an EPF driver configures a BAR as 64-bit,
> > even if the requested size is < 4 GB.
> > 
> > Respect the requested BAR configuration, just like how it is already
> > repected with regards to the prefetchable bit.
> 
> Does this (and the similar cadence patch) need a Fixes: tag for
> f25b5fae29d4?

I don't think so.

Both patches are about respecting the configuration requested by an EPF
driver.

So if an EPF driver requests a 64-bit BAR, the EPC driver should configure
that. (Regardless of the size that the EPF driver requests for the BAR.)

If we really want a Fixes-tag, I would imagine that it will be the respective
initial commits that added these drivers (pcie-cadence-ep.c and
pcie-rockchip-ep.c), as it has been this way since then.

If you look at the EPF drivers we currently have, they will currently only
request a 64-bit BAR if any of the BARs can only be configured as a 64-bit
BAR because of hardware limitiations.

$ git grep only_64bit

Neither of these two drivers have any such hardware limitiations,
so these commits are currently a bit pointless.

However, the drivers should of course do the right thing, because other
EPC drivers might look at them and copy their code.

And who knows, maybe sometime in the future there will be an EPF driver
that will explicitly request a 64-bit BAR, regardless of size.

TL;DR: I don't think these two commits are worth backporting.


> 
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> >  drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> > index c9046e97a1d2..57472cf48997 100644
> > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
> >  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
> >  	} else {
> >  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> > -		bool is_64bits = sz > SZ_2G;
> > +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
> >  
> >  		if (is_64bits && (bar & 1))
> >  			return -EINVAL;
> > -- 
> > 2.44.0
> >
Bjorn Helgaas April 12, 2024, 10 p.m. UTC | #5 
On Fri, Apr 12, 2024 at 11:39:39PM +0200, Niklas Cassel wrote:
> On Fri, Apr 12, 2024 at 12:51:27PM -0500, Bjorn Helgaas wrote:
> > On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> > > Ever since commit f25b5fae29d4 ("PCI: endpoint: Setting a BAR size > 4 GB
> > > is invalid if 64-bit flag is not set") it has been impossible to get the
> > > .set_bar() callback with a BAR size > 4 GB, if the BAR was also not
> > > requested to be configured as a 64-bit BAR.
> > > 
> > > It is however possible that an EPF driver configures a BAR as 64-bit,
> > > even if the requested size is < 4 GB.
> > > 
> > > Respect the requested BAR configuration, just like how it is already
> > > repected with regards to the prefetchable bit.
> > 
> > Does this (and the similar cadence patch) need a Fixes: tag for
> > f25b5fae29d4?
> 
> I don't think so.
> 
> Both patches are about respecting the configuration requested by an EPF
> driver.
> 
> So if an EPF driver requests a 64-bit BAR, the EPC driver should configure
> that. (Regardless of the size that the EPF driver requests for the BAR.)
> 
> If we really want a Fixes-tag, I would imagine that it will be the respective
> initial commits that added these drivers (pcie-cadence-ep.c and
> pcie-rockchip-ep.c), as it has been this way since then.
> 
> If you look at the EPF drivers we currently have, they will currently only
> request a 64-bit BAR if any of the BARs can only be configured as a 64-bit
> BAR because of hardware limitiations.
> 
> $ git grep only_64bit
> 
> Neither of these two drivers have any such hardware limitiations,
> so these commits are currently a bit pointless.
> 
> However, the drivers should of course do the right thing, because other
> EPC drivers might look at them and copy their code.
> 
> And who knows, maybe sometime in the future there will be an EPF driver
> that will explicitly request a 64-bit BAR, regardless of size.
> 
> TL;DR: I don't think these two commits are worth backporting.

OK, thanks!

> > > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > > ---
> > >  drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> > > index c9046e97a1d2..57472cf48997 100644
> > > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > > @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
> > >  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
> > >  	} else {
> > >  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> > > -		bool is_64bits = sz > SZ_2G;
> > > +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
> > >  
> > >  		if (is_64bits && (bar & 1))
> > >  			return -EINVAL;
> > > -- 
> > > 2.44.0
> > > 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
Niklas Cassel April 12, 2024, 10:02 p.m. UTC | #6 
On Fri, Apr 12, 2024 at 01:59:01PM -0500, Bjorn Helgaas wrote:
> On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> > ...
> 
> > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
> >  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
> >  	} else {
> >  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> > -		bool is_64bits = sz > SZ_2G;
> > +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
> >  
> >  		if (is_64bits && (bar & 1))
> >  			return -EINVAL;
> 
> Completely unrelated to *these* patches, but the BAR_CFG_CTRL
> definitions in both cadence and rockchip lead to some awkward case
> analysis:
> 
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS              0x4
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS     0x5
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS              0x6
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS     0x7
> 
>   if (is_64bits && is_prefetch)
>           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
>   else if (is_prefetch)
>           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
>   else if (is_64bits)
>           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
>   else
>           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
> 
> that *could* be just something like this:
> 
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM           0x4
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_64BITS        0x2
>   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH      0x1
> 
>   ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM;
>   if (is_64bits)
>     ctrl |= ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_64BITS;
>   if (is_prefetch)
>     ctrl |= ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH;


If you send the cleanup patches, I will send the Reviewed-by tags ;)


Kind regards,
Niklas
Bjorn Helgaas April 12, 2024, 10:11 p.m. UTC | #7 
On Sat, Apr 13, 2024 at 12:02:12AM +0200, Niklas Cassel wrote:
> On Fri, Apr 12, 2024 at 01:59:01PM -0500, Bjorn Helgaas wrote:
> > On Wed, Mar 13, 2024 at 11:58:00AM +0100, Niklas Cassel wrote:
> > > ...
> > 
> > > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > > @@ -153,7 +153,7 @@ static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
> > >  		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
> > >  	} else {
> > >  		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
> > > -		bool is_64bits = sz > SZ_2G;
> > > +		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
> > >  
> > >  		if (is_64bits && (bar & 1))
> > >  			return -EINVAL;
> > 
> > Completely unrelated to *these* patches, but the BAR_CFG_CTRL
> > definitions in both cadence and rockchip lead to some awkward case
> > analysis:
> > 
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS              0x4
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS     0x5
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS              0x6
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS     0x7
> > 
> >   if (is_64bits && is_prefetch)
> >           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
> >   else if (is_prefetch)
> >           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
> >   else if (is_64bits)
> >           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
> >   else
> >           ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
> > 
> > that *could* be just something like this:
> > 
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM           0x4
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_64BITS        0x2
> >   #define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH      0x1
> > 
> >   ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM;
> >   if (is_64bits)
> >     ctrl |= ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_64BITS;
> >   if (is_prefetch)
> >     ctrl |= ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH;
> 
> If you send the cleanup patches, I will send the Reviewed-by tags ;)

Fair enough :)
diff mbox series

Patch

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index c9046e97a1d2..57472cf48997 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -153,7 +153,7 @@  static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
 		ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
 	} else {
 		bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
-		bool is_64bits = sz > SZ_2G;
+		bool is_64bits = !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64);
 
 		if (is_64bits && (bar & 1))
 			return -EINVAL;