diff mbox series

[2/3] PCI: Create new reset method to force SBR for CXL

Message ID 20240311204132.62757-3-dave.jiang@intel.com
State New
Headers show
Series PCI: Add Secondary Bus Reset (SBR) support for CXL | expand

Commit Message

Dave Jiang March 11, 2024, 8:39 p.m. UTC 
CXL spec r3.1 8.1.5.2
By default Secondary Bus Reset (SBR) is masked for CXL ports. Introduce a
new PCI reset method "cxl_bus_force" to force SBR on CXL ports by setting
the unmask SBR bit in the CXL DVSEC port control register before performing
the bus reset and restore the original value of the bit post reset.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
 drivers/pci/pci.c   | 52 +++++++++++++++++++++++++++++++++++++++++++--
 include/linux/pci.h |  2 +-
 2 files changed, 51 insertions(+), 3 deletions(-)

Comments

Lukas Wunner March 12, 2024, 7:50 a.m. UTC | #1 
On Mon, Mar 11, 2024 at 01:39:54PM -0700, Dave Jiang wrote:
> CXL spec r3.1 8.1.5.2
> By default Secondary Bus Reset (SBR) is masked for CXL ports. Introduce a
> new PCI reset method "cxl_bus_force" to force SBR on CXL ports by setting
> the unmask SBR bit in the CXL DVSEC port control register before performing
> the bus reset and restore the original value of the bit post reset.

Hm, why not have a sysfs attribute (or sysctl variable) to unmask SBR?

That would avoid the need to touch pci code as the sysfs attribute could
be kept local to the cxl subsystem.

Thanks,

Lukas
diff mbox series

Patch

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 5e5550f54053..bbda7781f0f8 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5353,6 +5353,12 @@  static bool is_cxl_device(struct pci_dev *dev)
 					 CXL_DVSEC_PCIE_DEVICE);
 }
 
+static int cxl_port_dvsec(struct pci_dev *dev)
+{
+	return pci_find_dvsec_capability(dev, PCI_DVSEC_VENDOR_ID_CXL,
+					 CXL_DVSEC_PCIE_PORT);
+}
+
 static bool is_cxl_port_sbr_masked(struct pci_dev *dev)
 {
 	int dvsec;
@@ -5362,8 +5368,7 @@  static bool is_cxl_port_sbr_masked(struct pci_dev *dev)
 	/*
 	 * No DVSEC found, must not be CXL port.
 	 */
-	dvsec = pci_find_dvsec_capability(dev, PCI_DVSEC_VENDOR_ID_CXL,
-					  CXL_DVSEC_PCIE_PORT);
+	dvsec = cxl_port_dvsec(dev);
 	if (!dvsec)
 		return false;
 
@@ -5402,6 +5407,48 @@  static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
 	return pci_parent_bus_reset(dev, probe);
 }
 
+static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
+{
+	struct pci_dev *port_pdev;
+	int dvsec;
+	int rc;
+	u16 reg, val;
+
+	if (!is_cxl_device(dev))
+		return -ENODEV;
+
+	port_pdev = dev->bus->self;
+	if (!port_pdev)
+		return -ENODEV;
+
+	dvsec = cxl_port_dvsec(port_pdev);
+	if (!dvsec)
+		return -ENODEV;
+
+	if (probe)
+		return 0;
+
+	rc = pci_read_config_word(port_pdev, dvsec + CXL_DVSEC_PORT_CONTROL,
+				  &reg);
+	if (rc)
+		return -ENXIO;
+
+	if (!(reg & CXL_DVSEC_PORT_CONTROL_UNMASK_SBR)) {
+		val = reg | CXL_DVSEC_PORT_CONTROL_UNMASK_SBR;
+		pci_write_config_word(port_pdev,
+				      dvsec + CXL_DVSEC_PORT_CONTROL, val);
+	} else {
+		val = reg;
+	}
+
+	rc = pci_reset_bus_function(dev, probe);
+
+	if (reg != val)
+		pci_write_config_word(port_pdev, dvsec + CXL_DVSEC_PORT_CONTROL, reg);
+
+	return rc;
+}
+
 void pci_dev_lock(struct pci_dev *dev)
 {
 	/* block PM suspend, driver probe, etc. */
@@ -5486,6 +5533,7 @@  static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
 	{ pci_af_flr, .name = "af_flr" },
 	{ pci_pm_reset, .name = "pm" },
 	{ pci_reset_bus_function, .name = "bus" },
+	{ cxl_reset_bus_function, .name = "cxl_bus_force" },
 };
 
 static ssize_t reset_method_show(struct device *dev,
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7ab0d13672da..20c862c6b20f 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -51,7 +51,7 @@ 
 			       PCI_STATUS_PARITY)
 
 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
-#define PCI_NUM_RESET_METHODS 7
+#define PCI_NUM_RESET_METHODS 8
 
 #define PCI_RESET_PROBE		true
 #define PCI_RESET_DO_RESET	false