| Message ID | 20240129-x1e80100-pci-v2-1-a466d10685b6@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: qcom: Add PCIe support for X1E80100 | expand |
On 29/01/2024 12:10, Abel Vesa wrote: > Document the PCIe Controllers on the X1E80100 platform. They are similar > to the ones found on SM8550, but they don't have SF QTB clock. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. Tools like b4 or scripts_getmaintainer.pl provide you proper list of people, so fix your workflow. Tools might also fail if you work on some ancient tree (don't, use mainline), work on fork of kernel (don't, use mainline) or you ignore some maintainers (really don't). Just use b4 and all the problems go away. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof
On 24-01-29 15:19:46, Krzysztof Kozlowski wrote: > On 29/01/2024 12:10, Abel Vesa wrote: > > Document the PCIe Controllers on the X1E80100 platform. They are similar > > to the ones found on SM8550, but they don't have SF QTB clock. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel. > > Tools like b4 or scripts_getmaintainer.pl provide you proper list of > people, so fix your workflow. Tools might also fail if you work on some > ancient tree (don't, use mainline), work on fork of kernel (don't, use > mainline) or you ignore some maintainers (really don't). Just use b4 and > all the problems go away. > > You missed at least devicetree list (maybe more), so this won't be > tested by automated tooling. Performing review on untested code might be > a waste of time. Oups, forgot to run "b4 prep --auto-to-cc" after I added the bindings patch. Sorry about that. Will resend v2. > > Please kindly resend and include all necessary To/Cc entries. > > > Best regards, > Krzysztof >
On Mon, Jan 29, 2024 at 01:10:26PM +0200, Abel Vesa wrote: > Document the PCIe Controllers on the X1E80100 platform. They are similar > to the ones found on SM8550, but they don't have SF QTB clock. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index a93ab3b54066..7381e38b7398 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -41,6 +41,7 @@ properties: > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > - qcom,pcie-sm8550 > + - qcom,pcie-x1e80100 > - items: > - enum: > - qcom,pcie-sm8650 > @@ -227,6 +228,7 @@ allOf: > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > - qcom,pcie-sm8550 > + - qcom,pcie-x1e80100 > then: > properties: > reg: > @@ -826,6 +828,32 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-x1e80100 > + then: > + properties: > + clocks: > + maxItems: 7 > + clock-names: > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: noc_aggr # Aggre NoC PCIe AXI clock > + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: pci # PCIe core reset > + - const: link_down # PCIe link down reset > + > - if: > properties: > compatible: > @@ -884,6 +912,7 @@ allOf: > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > - qcom,pcie-sm8550 > + - qcom,pcie-x1e80100 > then: > oneOf: > - properties: > > -- > 2.34.1 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..7381e38b7398 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -41,6 +41,7 @@ properties: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 - items: - enum: - qcom,pcie-sm8650 @@ -227,6 +228,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: properties: reg: @@ -826,6 +828,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-x1e80100 + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + resets: + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + - if: properties: compatible: @@ -884,6 +912,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: oneOf: - properties:
Document the PCIe Controllers on the X1E80100 platform. They are similar to the ones found on SM8550, but they don't have SF QTB clock. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+)