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Box" To: mika.westerberg@linux.intel.com, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com, rjw@rjwysocki.net Cc: tasev.stefanoska@skynet.be, enriquezmark36@gmail.com, kernel@witt.link, wse@tuxedocomputers.com, vidyas@nvidia.com, kai.heng.feng@canonical.com, sathyanarayanan.kuppuswamy@linux.intel.com, ricky_wu@realtek.com, mario.limonciello@amd.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] PCI: Create function to save L1SS offset Date: Sun, 28 Jan 2024 15:32:09 -0800 Message-Id: <20240128233212.1139663-3-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128233212.1139663-1-david.e.box@linux.intel.com> References: <20240128233212.1139663-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The offset for the L1 Substate Capability register is not saved in pci_dev until pci_configure_ltr() which only builds with CONFIG_PCIEASPM. Instead, create a separate function to retrieve the offset so that it is always available. This offset will be used to save and restore the L1SS registers even when PCIEASPM=n. Signed-off-by: David E. Box --- drivers/pci/pci.h | 1 + drivers/pci/pcie/aspm.c | 9 ++++++--- drivers/pci/probe.c | 1 + include/linux/pci.h | 4 ++-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 6771862de921..b48e8e4f360f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -97,6 +97,7 @@ void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); +void pci_aspm_get_l1ss(struct pci_dev *pdev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); static inline void pci_wakeup_event(struct pci_dev *dev) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 6d077e237a65..93718b733af3 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -24,6 +24,12 @@ #include "../pci.h" +void pci_aspm_get_l1ss(struct pci_dev *pdev) +{ + /* Read L1 PM substate capabilities */ + pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); +} + #ifdef CONFIG_PCIEASPM #ifdef MODULE_PARAM_PREFIX @@ -970,9 +976,6 @@ void pci_configure_ltr(struct pci_dev *pdev) if (!pci_is_pcie(pdev)) return; - /* Read L1 PM substate capabilities */ - pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_LTR)) return; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 0b8c2c9cc9dd..e39ad912ce8c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2208,6 +2208,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev, NULL); pci_configure_relaxed_ordering(dev); + pci_aspm_get_l1ss(dev); pci_configure_ltr(dev); pci_configure_eetlp_prefix(dev); pci_configure_serr(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index dea043bc1e38..dfc4b525c7a1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -390,9 +390,9 @@ struct pci_dev { unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ -#ifdef CONFIG_PCIEASPM - struct pcie_link_state *link_state; /* ASPM link state */ u16 l1ss; /* L1SS Capability pointer */ +#ifdef CONFIG_PCIEASPM + struct pcie_link_state *link_state; /* ASPM link state */ unsigned int ltr_path:1; /* Latency Tolerance Reporting supported from root to here */ #endif