From patchwork Fri Aug 25 09:32:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1825881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4RXFBB4sLwz1yfF for ; Fri, 25 Aug 2023 19:33:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244304AbjHYJcq (ORCPT ); Fri, 25 Aug 2023 05:32:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244259AbjHYJca (ORCPT ); Fri, 25 Aug 2023 05:32:30 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 548731FE9; Fri, 25 Aug 2023 02:32:27 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.02,195,1688396400"; d="scan'208";a="173961370" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2023 18:32:24 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C82C340134E8; Fri, 25 Aug 2023 18:32:24 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v20 12/19] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Date: Fri, 25 Aug 2023 18:32:12 +0900 Message-Id: <20230825093219.2685912-13-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230825093219.2685912-1-yoshihiro.shimoda.uh@renesas.com> References: <20230825093219.2685912-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Renesas R-Car Gen4 PCIe controllers require vendor-specific initialization before .init(). To use dw->dbi and dw->num-lanes in the initialization code, introduce .pre_init() into struct dw_pcie_ep_ops. Also introduce .deinit() to disable the controller by using vendor-specific de-initialization. Note that the ep_init in the struct dw_pcie_ep_ops should be renamed to init later. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin --- drivers/pci/controller/dwc/pcie-designware-ep.c | 12 +++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 6eb897572d2b..aac0e5263f97 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -695,6 +695,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) epc->mem->window.page_size); pci_epc_mem_exit(epc); + + if (ep->ops->deinit) + ep->ops->deinit(ep); } EXPORT_SYMBOL_GPL(dw_pcie_ep_exit); @@ -798,6 +801,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->phys_base = res->start; ep->addr_size = resource_size(res); + if (ep->ops->pre_init) + ep->ops->pre_init(ep); + dw_pcie_version_detect(pci); dw_pcie_iatu_detect(pci); @@ -852,7 +858,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->page_size); if (ret < 0) { dev_err(dev, "Failed to initialize address space\n"); - return ret; + goto err_ep_deinit; } ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, @@ -898,6 +904,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) err_exit_epc_mem: pci_epc_mem_exit(epc); +err_ep_deinit: + if (ep->ops->deinit) + ep->ops->deinit(ep); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_ep_init); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index c7759a508ca9..b5040440b7c0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -343,7 +343,9 @@ struct dw_pcie_rp { }; struct dw_pcie_ep_ops { + void (*pre_init)(struct dw_pcie_ep *ep); void (*ep_init)(struct dw_pcie_ep *ep); + void (*deinit)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num); const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);