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Thu, 13 Oct 2022 11:40:18 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 12/21] PCI: tegra194: Enable DMA interrupt Date: Fri, 14 Oct 2022 00:08:45 +0530 Message-ID: <20221013183854.21087-13-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT074:EE_|DM4PR12MB6568:EE_ X-MS-Office365-Filtering-Correlation-Id: 02db9b6d-fa3c-4d5b-76cf-08daad4a6764 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T8ujoV2wIcLBb9jzuOlqb/HDbNjMhUeJE9w6uZIJIT0X/dJRijyZUIiMJnT9Y1ZMHbKI7eBFjyzh7mfYgRA3ZEjY314mEUoihbcamYDAf74c0/CrhQTPXnrMsvC0rJa1AyX1IUHljo9om/O/mQMfnl0Lj3PaPgrIcZ4DrhN43rY3LoFAN9e58f/x3zkyZ72PTZm4hhpd6yvKr7ZGMJOOPWQuR/ova1CA4608h9RP/cdQnOLCLlaP7DLRGmGZ139e1yecOUECX5EdaHGNmnGCfK4SoGGRLha7y8Am0vxvGRbZCxO8sjKik1y/yMo+y7cQlCfO8RiBgDf2XRBEgPu76x3N87rFJ3PqLmew5trA6cGkIg4yDrAgFAxdkLOroU9qxOCG3uZeJZSu+CSoGJUX1Tbo8pD7Za7cZmw8FurUL9kwK+6w3tuOCLkh3kCCsRyPrWWquLvr4jN/PRqk1KJxwmLSxaf48Xh4/1+2Wxx7q9lh3Aayeykcui66Z3YCLWMwbd9Vm8+hTGMQaG4D/9ML/yuF+JZrCtwkLAStYzIsLAqz+UURhgQiYyRBdus3YKOswGILzUGgdN1djlfYyQA74D5sU7u4RpWuKm1rAgkzkAUFc3TFqoqnqwTqkB3SQMXjciVwevJhBHM4Kgzp7wCZpZ7T9EOF/GCXQ8x7hyRtCw3i6JZ9ZWxW2BCAMrcvBDKzqvi4QDv2cyabKWB+/U9gpQsIATOAPLUlGiv1wxVB2eAXwRAAEozh8XE2z3TmDK/J4v3otnsb2ktctIM2V/2gqdV9ayyZyEIDhNJNZ8qK2z4= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199015)(40470700004)(46966006)(36840700001)(5660300002)(7416002)(1076003)(186003)(336012)(2616005)(7636003)(2906002)(356005)(41300700001)(26005)(8936002)(7696005)(426003)(921005)(82310400005)(86362001)(40460700003)(36756003)(47076005)(40480700001)(82740400003)(36860700001)(316002)(110136005)(54906003)(478600001)(70206006)(8676002)(70586007)(4326008)(6666004);DIR:OUT;SFP:1101; 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Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 786e5d5f43b9..a1c3481585c9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -94,6 +94,7 @@ #define APPL_INTR_EN_L1_8_0 0x44 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) +#define APPL_INTR_EN_L1_8_EDMA_INT_EN BIT(6) #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) @@ -552,6 +553,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) spurious = 0; } + if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) { + status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); + /* Interrupt is handled by dma driver, don't treat it as spurious */ + if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) + spurious = 0; + } + if (spurious) { dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", status_l0); @@ -781,6 +789,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp) val |= APPL_INTR_EN_L1_8_INTX_EN; val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; + val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; if (IS_ENABLED(CONFIG_PCIEAER)) val |= APPL_INTR_EN_L1_8_AER_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); @@ -1927,6 +1936,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; + val |= APPL_INTR_EN_L0_0_INT_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L0_0); val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); @@ -1934,6 +1944,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); + val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); + val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; + appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); + reset_control_deassert(pcie->core_rst); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);