| Message ID | 20220910063045.16648-12-manivannan.sadhasivam@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Improvements to the Qcom PCIe Endpoint driver | expand |
On Sat, 10 Sep 2022 12:00:44 +0530, Manivannan Sadhasivam wrote: > Add devicetree bindings support for SM8450 SoC. Only the clocks are > different on this platform, rest is same as SDX55. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++-- > 1 file changed, 36 insertions(+), 3 deletions(-) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ pcie-ep@40000000: qcom,perst-regs:0: [27] is too short arch/arm/boot/dts/qcom-sdx55-mtp.dtb pcie-ep@40000000: qcom,perst-regs:0: [28] is too short arch/arm/boot/dts/qcom-sdx55-t55.dtb arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dtb pcie-ep@40000000: Unevaluated properties are not allowed ('qcom,perst-regs' was unexpected) arch/arm/boot/dts/qcom-sdx55-mtp.dtb arch/arm/boot/dts/qcom-sdx55-t55.dtb arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dtb
On 10/09/2022 16:53, Rob Herring wrote: > On Sat, 10 Sep 2022 12:00:44 +0530, Manivannan Sadhasivam wrote: >> Add devicetree bindings support for SM8450 SoC. Only the clocks are >> different on this platform, rest is same as SDX55. >> >> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> >> --- >> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++-- >> 1 file changed, 36 insertions(+), 3 deletions(-) >> > > Running 'make dtbs_check' with the schema in this patch gives the > following warnings. Consider if they are expected or the schema is > incorrect. These may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for dtbs_check. > This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/patch/ > > > pcie-ep@40000000: qcom,perst-regs:0: [27] is too short > arch/arm/boot/dts/qcom-sdx55-mtp.dtb This is independent issue. I'll fix it. Best regards, Krzysztof
On Sat, 10 Sep 2022 12:00:44 +0530, Manivannan Sadhasivam wrote: > Add devicetree bindings support for SM8450 SoC. Only the clocks are > different on this platform, rest is same as SDX55. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++-- > 1 file changed, 36 insertions(+), 3 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index bb8e982e69be..977c976ea799 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: qcom,sdx55-pcie-ep + enum: + - qcom,sdx55-pcie-ep + - qcom,sm8450-pcie-ep reg: items: @@ -32,10 +34,12 @@ properties: - const: mmio clocks: - maxItems: 7 + minItems: 7 + maxItems: 8 clock-names: - maxItems: 7 + minItems: 7 + maxItems: 8 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -124,6 +128,35 @@ allOf: - const: sleep - const: ref + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Reference clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ref + - const: ddrss_sf_tbu + - const: aggre_noc_axi + unevaluatedProperties: false examples:
Add devicetree bindings support for SM8450 SoC. Only the clocks are different on this platform, rest is same as SDX55. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++-- 1 file changed, 36 insertions(+), 3 deletions(-)