| Message ID | 20220629141000.18111-8-johan+linaro@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: qcom: Add support for SC8280XP and SA8540P | expand |
On Wed, Jun 29, 2022 at 04:09:57PM +0200, Johan Hovold wrote: > The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane > and one 1-lane. > > Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. > > Note that like for SC8280XP, the SA8540 controllers need two or three > interconnect clocks to be enabled. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org>
On Wed, Jun 29, 2022 at 04:09:57PM +0200, Johan Hovold wrote: > The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane > and one 1-lane. > > Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. > > Note that like for SC8280XP, the SA8540 controllers need two or three > interconnect clocks to be enabled. > > Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index da3f1cdc4ba6..8ab88e5743da 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1461,6 +1461,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { > .ops = &ops_2_4_0, > }; > > +static const struct qcom_pcie_cfg sa8540p_cfg = { > + .ops = &ops_1_9_0, > + .has_ddrss_sf_tbu_clk = true, > +}; > + > static const struct qcom_pcie_cfg sc8280xp_cfg = { > .ops = &ops_1_9_0, > .has_ddrss_sf_tbu_clk = true, > @@ -1626,6 +1631,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg }, > { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, > { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, > + { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg }, > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > -- > 2.35.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index da3f1cdc4ba6..8ab88e5743da 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1461,6 +1461,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { .ops = &ops_2_4_0, }; +static const struct qcom_pcie_cfg sa8540p_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, +}; + static const struct qcom_pcie_cfg sc8280xp_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, @@ -1626,6 +1631,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg }, { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg }, { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg }, + { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg }, { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. Note that like for SC8280XP, the SA8540 controllers need two or three interconnect clocks to be enabled. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+)