From patchwork Mon Aug 23 16:40:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1519839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=VneIWHy9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GtdKY4x1kz9sWc for ; Tue, 24 Aug 2021 02:41:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbhHWQlq (ORCPT ); Mon, 23 Aug 2021 12:41:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:37272 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229904AbhHWQlp (ORCPT ); Mon, 23 Aug 2021 12:41:45 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 105C7613B1; Mon, 23 Aug 2021 16:41:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629736863; bh=cEI+qg5LiFT/MsVm3juyQ/F0QofSoSmzQNAz+sFwK+M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VneIWHy9+of7BwhH4vDz9D8npklTIPXWHDLOwbRSoGn6oUWAVKXbkx722Td0Ntzkb PVqsnohDZKW5lr1e6IX2yPfsKkykdqbNxJIjW3nMAFXpGUgbvieFYi+IzKxGrM3gOr bhMv/J5eq99dAZWiQv24w/KI+k+bayyj7ouR8tfJ0rr3ckY6pv0+MGHO60AF8LXjDJ Q0f/VSq+Ow2Tv1Yp0CZLF8bJWF+4EjMgSPQh1GP0lOnnasal8sv7XPUvy3oIvNBdmp E/+47t12KriOP3MaSPNssRBXlV2EzeT6BYzWVgtNp0iMFbu108S8CFXF7Tv1bnTjPM s4EBnXRh6m/0w== Received: by pali.im (Postfix) id 24CCA251E; Mon, 23 Aug 2021 18:41:01 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , =?utf-8?q?Marek_Be?= =?utf-8?q?h=C3=BAn?= , "Marc Zyngier" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] PCI: aardvark: Fix reading MSI interrupt number Date: Mon, 23 Aug 2021 18:40:31 +0200 Message-Id: <20210823164033.27491-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210823164033.27491-1-pali@kernel.org> References: <20210815103624.19528-1-pali@kernel.org> <20210823164033.27491-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Experiments showed that in register PCIE_MSI_PAYLOAD_REG is stored number of the last received MSI interrupt and not number of MSI interrupt which belongs to msi_idx bit. Therefore this implies that aardvark HW can cache only bits [4:0] of received MSI interrupts with effectively means that it supports only MSI interrupts with numbers 0-31. Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt number. Instead ensure that pci-aardvark.c configures only MSI numbers in range 0-31 and then msi_idx contains correct received MSI number. Signed-off-by: Pali Rohár Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 48fbfa7eb24c..81c4a9ff91a3 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1232,7 +1232,6 @@ static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) static void advk_pcie_handle_msi(struct advk_pcie *pcie) { u32 msi_val, msi_mask, msi_status, msi_idx; - u16 msi_data; int virq; msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); @@ -1243,17 +1242,13 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) if (!(BIT(msi_idx) & msi_status)) continue; - /* - * msi_idx contains bits [4:0] of the msi_data and msi_data - * contains 16bit MSI interrupt number from MSI inner domain - */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); - msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; - virq = irq_find_mapping(pcie->msi_inner_domain, msi_data); + + virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx); if (virq) generic_handle_irq(virq); else - dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%04hx\n", msi_data); + dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); } advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,