diff mbox series

dt-bindings: PCI: intel,lgm-pcie: Add reference to common schemas

Message ID 20210719220351.2662758-1-robh@kernel.org
State New
Headers show
Series dt-bindings: PCI: intel,lgm-pcie: Add reference to common schemas | expand

Commit Message

Rob Herring (Arm) July 19, 2021, 10:03 p.m. UTC 
Add a reference to snps,dw-pcie.yaml (and indirectly pci-bus.yaml) schemas.
With this, the common bus properties can be dropped from the schema.

Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: linux-pci@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
This applies on top of Mauro's snps,dw-pcie.yaml series which I've 
applied to the DT tree.

 .../bindings/pci/intel-gw-pcie.yaml           | 34 +++----------------
 1 file changed, 4 insertions(+), 30 deletions(-)

Comments

Rob Herring (Arm) July 19, 2021, 10:12 p.m. UTC | #1 
On Mon, Jul 19, 2021 at 4:03 PM Rob Herring <robh@kernel.org> wrote:
>
> Add a reference to snps,dw-pcie.yaml (and indirectly pci-bus.yaml) schemas.
> With this, the common bus properties can be dropped from the schema.
>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Dilip Kota <eswara.kota@linux.intel.com>

While at it, I'll change to a non-bouncing address for LGM SoC[1]:
Rahul Tanwar <rtanwar@maxlinear.com>

Rob

[1] https://lkml.org/lkml/2021/3/16/282
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
index a1e2be737eec..e15730d31274 100644
--- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
@@ -17,21 +17,15 @@  select:
   required:
     - compatible
 
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
 properties:
   compatible:
     items:
       - const: intel,lgm-pcie
       - const: snps,dw-pcie
 
-  device_type:
-    const: pci
-
-  "#address-cells":
-    const: 3
-
-  "#size-cells":
-    const: 2
-
   reg:
     items:
       - description: Controller control and status registers.
@@ -62,30 +56,13 @@  properties:
   reset-gpios:
     maxItems: 1
 
-  linux,pci-domain: true
-
   num-lanes:
     maximum: 2
-    description: Number of lanes to use for this port.
-
-  '#interrupt-cells':
-    const: 1
-
-  interrupt-map-mask:
-    description: Standard PCI IRQ mapping properties.
-
-  interrupt-map:
-    description: Standard PCI IRQ mapping properties.
 
   max-link-speed:
-    description: Specify PCI Gen for link capability.
-    $ref: /schemas/types.yaml#/definitions/uint32
     enum: [1, 2, 3, 4]
     default: 1
 
-  bus-range:
-    description: Range of bus numbers associated with this controller.
-
   reset-assert-ms:
     description: |
       Delay after asserting reset to the PCIe device.
@@ -94,9 +71,6 @@  properties:
 
 required:
   - compatible
-  - device_type
-  - "#address-cells"
-  - "#size-cells"
   - reg
   - reg-names
   - ranges
@@ -109,7 +83,7 @@  required:
   - interrupt-map
   - interrupt-map-mask
 
-additionalProperties: false
+unevaluatedProperties: false
 
 examples:
   - |