diff mbox series

Bug fix: 500ms is not enough for pcie training

Message ID 20210419112218.10921-1-jinsiyu940203@163.com
State New
Headers show
Series Bug fix: 500ms is not enough for pcie training | expand

Commit Message

Siyu Jin April 19, 2021, 11:22 a.m. UTC 
---
 drivers/pci/controller/pcie-rockchip-host.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--
2.17.1

Comments

Bjorn Helgaas April 20, 2021, 1:42 p.m. UTC | #1 
[+cc rockchip maintainers]

On Mon, Apr 19, 2021 at 07:22:18PM +0800, Siyu Jin wrote:

Thanks for this.  Before this can be applied:

- Run "git log --oneline drivers/pci/controller/pcie-rockchip-host.c"
  and make your subject line match in structure and style.

- Add a commit log.  It should explain the problem this fixes.  Since
  this changes a timeout, you should be able to cite something in the
  spec (either the PCIe spec or the Rockchip spec) that describes the
  time needed.

- Add a signed-off-by: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?id=v5.11#n361

- CC the relevant maintainers (use ./scripts/get_maintainer.pl)

> ---
>  drivers/pci/controller/pcie-rockchip-host.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index f1d08a1b1591..9da831b2b7c2 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -332,7 +332,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
>  	/* 500ms timeout value should be enough for Gen1/2 training */
>  	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
>  				 status, PCIE_LINK_UP(status), 20,
> -				 500 * USEC_PER_MSEC);
> +				 1000 * USEC_PER_MSEC);
>  	if (err) {
>  		dev_err(dev, "PCIe link training gen1 timeout!\n");
>  		goto err_power_off_phy;
> @@ -349,7 +349,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
> 
>  		err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
>  					 status, PCIE_LINK_IS_GEN2(status), 20,
> -					 500 * USEC_PER_MSEC);
> +					 1000 * USEC_PER_MSEC);
>  		if (err)
>  			dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
>  	}
> --
> 2.17.1
>
diff mbox series

Patch

diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index f1d08a1b1591..9da831b2b7c2 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -332,7 +332,7 @@  static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
 				 status, PCIE_LINK_UP(status), 20,
-				 500 * USEC_PER_MSEC);
+				 1000 * USEC_PER_MSEC);
 	if (err) {
 		dev_err(dev, "PCIe link training gen1 timeout!\n");
 		goto err_power_off_phy;
@@ -349,7 +349,7 @@  static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)

 		err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
 					 status, PCIE_LINK_IS_GEN2(status), 20,
-					 500 * USEC_PER_MSEC);
+					 1000 * USEC_PER_MSEC);
 		if (err)
 			dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
 	}