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Wed, 7 Apr 2021 03:03:38 +0000 From: Zhiqiang Hou To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, leoyang.li@nxp.com, gustavo.pimentel@synopsys.com Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, Hou Zhiqiang Subject: [PATCHv5 1/6] PCI: layerscape: Change to use the DWC common link-up check function Date: Wed, 7 Apr 2021 11:09:43 +0800 Message-Id: <20210407030948.3845-2-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210407030948.3845-1-Zhiqiang.Hou@nxp.com> References: <20210407030948.3845-1-Zhiqiang.Hou@nxp.com> X-Originating-IP: [119.31.174.73] X-ClientProxiedBy: MA1PR01CA0156.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::26) To HE1PR0402MB3371.eurprd04.prod.outlook.com (2603:10a6:7:85::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.73) by MA1PR01CA0156.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:71::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4020.17 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Og219T1YiS2RunU/uTeQIaVEOHJQF37130RAA1VjF+GbHattbFVywjimfufBFzvUSJ70JnVmfKmCenAVU4XpV57AUOoL17PNc76Xoabh4tvtDKp3PXb1X12IoVEfh/oTwGKfP++6goKwFN2wO08G+ZDzepRaitvkSIpYi2hEWE/S/XSLmiD1bCJj0XqMDFraAhvsPCQ7pBU1U9IW0KxOl7rTXxXPUWVkDjGUJrBK+EoL5dBpCkNuFyjaQVZJ0dFatCJ5zu9RhoIj84rWmhhgXAeHuprNrXJBVFlO9hdqKsbatO+9YsGHAzEJwqvgwU3LJTyY3wPSIOHdL8Aqx8X7dKh2tfB6E+lob8bSbCF/MIigo7aMIfr0OByedmAhZ0C7rSG4odX2jOxL3u8Kz/05212O598qsOeUp9yDPnr3bT9HNAyR8RpgmrHFSX1Qgks4IlM4mQ20ClOC+9/mcQkhEFtVsqarLWXQjY/eDdXh5HbctCWrFm0wlQWkuIj85Ojnz8KxNfMVj332bmM+iGFoaOeyiu/LCojpWnFu3vo8tUxpcG7stxujgWDCM+NLjXZt7YtDCTkEhOQWWa/9zIC83NlQKDCZicQ8BIeW3w3uN+AXNgJdG9nraC3IoC/KRjtJg3JOMsvTz2iA3ytb22Ouj7UGcA3MeSPKkY9B+1HEO558+hSyhPU3AgrOf+LSobSyvqz80zuFurIJwG4wiQ7zG/NNkQQ+Bk+CeCMZSqS+dUWjQE/Duu1BNqMM+YHKKMcKkZ47UEKkVMjdABffthSytFnx/wRGcOHLu7SBV2B0Oxz6100kYzCe8f6vozj3yI5uKHKf5Vzb788EV0EwYC11S6CF4wVxbgSVow5zCgjO1/QFR6Piv0mjSKb9eBpwc7SHfhbY+9SpoKwedmU4giG0SQN7AzEnxFtFQgi/RoCeh3MEbRa9j9rGbUmcm9vtStPtv4rH8UGaeBiUTnynHxFQohnfzdlB8JbeCWv9xBKgvyXwWfgdNAdnlqhN2bjWn3PhaJ5BrFjufTYvANw8aR4Oowu8NY0EMgFHdDAJtNEDNZlB0M50lI88BdRi0Fbuo54D00UTM+rjJgQfc4reQ9Hl9ULOB4MnPSxO8ZcWr6Yy9gH875byTA1kC3kvERPqL+HOkzAnHYX3QGNWyb0rY9BU7/gMSag0E+9qkaED994jxJOwZIgh4TJRTkODnjjwBtrRGkTgOP+zImHOYEAGNR4HA92vr7YyT1+yN9u1l4D+SU69jSRatGz5kZTweSDAEq1Ku3/UrNyYeUNK5/TW5CPDGTr2AtraIlwKiOmOXLscm9UwzYPvI40edmGfx9OUx738 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6b546b9-020c-4f4c-c4ea-08d8f971bd51 X-MS-Exchange-CrossTenant-AuthSource: HE1PR0402MB3371.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2021 03:03:38.0195 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: d5qQ8jkG/glxBjnhad9D9tIQzwc3ZtNIEHGv0613RnflykYywJhHZfjEf70C4cav67PPnECkVQN0u/xeREO0Ig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR04MB3276 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang The current Layerscape PCIe driver directly uses the physical layer LTSSM code to check the link-up state, which treats the > L0 states as link-up. This is not correct, since there is not explicit map between link-up state and LTSSM. So this patch changes to use the DWC common link-up check function. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- V5: - No change drivers/pci/controller/dwc/pci-layerscape.c | 140 ++------------------ 1 file changed, 10 insertions(+), 130 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 5b9c625df7b8..71911ca4c589 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -22,12 +22,6 @@ #include "pcie-designware.h" -/* PEX1/2 Misc Ports Status Register */ -#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) -#define LTSSM_STATE_SHIFT 20 -#define LTSSM_STATE_MASK 0x3f -#define LTSSM_PCIE_L0 0x11 /* L0 state */ - /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ @@ -36,19 +30,12 @@ #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { - u32 lut_offset; - u32 ltssm_shift; - u32 lut_dbg; const struct dw_pcie_host_ops *ops; - const struct dw_pcie_ops *dw_pcie_ops; }; struct ls_pcie { struct dw_pcie *pci; - void __iomem *lut; - struct regmap *scfg; const struct ls_pcie_drvdata *drvdata; - int index; }; #define to_ls_pcie(x) dev_get_drvdata((x)->dev) @@ -83,38 +70,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) iowrite32(val, pci->dbi_base + PCIE_STRFMR1); } -static int ls1021_pcie_link_up(struct dw_pcie *pci) -{ - u32 state; - struct ls_pcie *pcie = to_ls_pcie(pci); - - if (!pcie->scfg) - return 0; - - regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); - state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; - - return 1; -} - -static int ls_pcie_link_up(struct dw_pcie *pci) -{ - struct ls_pcie *pcie = to_ls_pcie(pci); - u32 state; - - state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> - pcie->drvdata->ltssm_shift) & - LTSSM_STATE_MASK; - - if (state < LTSSM_PCIE_L0) - return 0; - - return 1; -} - /* Forward error response of outbound non-posted requests */ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) { @@ -139,96 +94,24 @@ static int ls_pcie_host_init(struct pcie_port *pp) return 0; } -static int ls1021_pcie_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct ls_pcie *pcie = to_ls_pcie(pci); - struct device *dev = pci->dev; - u32 index[2]; - int ret; - - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - ret = PTR_ERR(pcie->scfg); - dev_err(dev, "No syscfg phandle specified\n"); - pcie->scfg = NULL; - return ret; - } - - if (of_property_read_u32_array(dev->of_node, - "fsl,pcie-scfg", index, 2)) { - pcie->scfg = NULL; - return -EINVAL; - } - pcie->index = index[1]; - - return ls_pcie_host_init(pp); -} - -static const struct dw_pcie_host_ops ls1021_pcie_host_ops = { - .host_init = ls1021_pcie_host_init, -}; - static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, }; -static const struct dw_pcie_ops dw_ls1021_pcie_ops = { - .link_up = ls1021_pcie_link_up, -}; - -static const struct dw_pcie_ops dw_ls_pcie_ops = { - .link_up = ls_pcie_link_up, -}; - -static const struct ls_pcie_drvdata ls1021_drvdata = { - .ops = &ls1021_pcie_host_ops, - .dw_pcie_ops = &dw_ls1021_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls1043_drvdata = { - .lut_offset = 0x10000, - .ltssm_shift = 24, - .lut_dbg = 0x7fc, +static const struct ls_pcie_drvdata layerscape_drvdata = { .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls1046_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 24, - .lut_dbg = 0x407fc, - .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls2080_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, - .lut_dbg = 0x7fc, - .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, -}; - -static const struct ls_pcie_drvdata ls2088_drvdata = { - .lut_offset = 0x80000, - .ltssm_shift = 0, - .lut_dbg = 0x407fc, - .ops = &ls_pcie_host_ops, - .dw_pcie_ops = &dw_ls_pcie_ops, }; static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata }, - { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, - { .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, - { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, - { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, - { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, - { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata }, - { .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata }, + { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1021a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata }, { }, }; @@ -250,7 +133,6 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->ops = pcie->drvdata->dw_pcie_ops; pci->pp.ops = pcie->drvdata->ops; pcie->pci = pci; @@ -260,8 +142,6 @@ static int ls_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset; - if (!ls_pcie_is_bridge(pcie)) return -ENODEV;