From patchwork Mon Feb 1 19:58:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 1434320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=V/+1mANR; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DTzNq4Z2Rz9tjs for ; Tue, 2 Feb 2021 07:01:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232964AbhBAUBV (ORCPT ); Mon, 1 Feb 2021 15:01:21 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:41956 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230273AbhBAUBN (ORCPT ); Mon, 1 Feb 2021 15:01:13 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 111JxMfJ024071; Mon, 1 Feb 2021 13:59:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1612209562; bh=Hv2Bn0Lk5Are5SnuuKfQMZlyBMtzlQMuYQhqnCaXHzc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=V/+1mANRFmE8sVMBi1sd3q6HlKRw2AVKhrgXIXLFkyBDFUohY6Kw+wB207ImH9t3I DnwHSpRwYRyWJGrkYH9Al7uru3fVQVzG/8yuMFwe0HY5R1IWRszvQmilndPSTRoxzQ gd2ZNSEIQYpinfKTMYa++Fd6Wnf3hhEHoED3uZz8= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 111JxMKv101912 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 1 Feb 2021 13:59:22 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 1 Feb 2021 13:59:22 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 1 Feb 2021 13:59:22 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 111JwAQj085814; Mon, 1 Feb 2021 13:59:17 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Jonathan Corbet , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann , Jon Mason , Dave Jiang , Allen Hubbe , Tom Joseph , Rob Herring CC: Greg Kroah-Hartman , , , , Subject: [PATCH v11 12/17] PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_map Date: Tue, 2 Feb 2021 01:28:04 +0530 Message-ID: <20210201195809.7342-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210201195809.7342-1-kishon@ti.com> References: <20210201195809.7342-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The number of functions supported by the endpoint controller is configured in LM_EP_FUNC_CFG based on func_no member of struct pci_epf. Now that an endpoint function can be associated with two endpoint controllers (primary and secondary), just using func_no will not suffice as that will take into account only if the endpoint controller is associated with the primary interface of endpoint function. Instead use epc->function_num_map which will already have the configured functions information (irrespective of whether the endpoint controller is associated with primary or secondary interface). Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Tom Joseph --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index dc88078194cb..897cdde02bd8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -506,18 +506,13 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; struct device *dev = pcie->dev; - struct pci_epf *epf; - u32 cfg; int ret; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. */ - cfg = BIT(0); - list_for_each_entry(epf, &epc->pci_epf, list) - cfg |= BIT(epf->func_no); - cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); + cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map); ret = cdns_pcie_start_link(pcie); if (ret) {