diff mbox series

[v1] PCI: controller: convert to devm_platform_ioremap_resource_byname()

Message ID 20200601143345.24965-1-zhengdejin5@gmail.com
State New
Headers show
Series [v1] PCI: controller: convert to devm_platform_ioremap_resource_byname() | expand

Commit Message

Dejin Zheng June 1, 2020, 2:33 p.m. UTC
Use devm_platform_ioremap_resource_byname() to simplify codes.
it contains platform_get_resource_byname() and devm_ioremap_resource().

Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
---
 drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
 drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
 drivers/pci/controller/pci-tegra.c                 | 8 +++-----
 drivers/pci/controller/pci-xgene.c                 | 3 +--
 drivers/pci/controller/pcie-altera-msi.c           | 3 +--
 drivers/pci/controller/pcie-altera.c               | 9 +++------
 drivers/pci/controller/pcie-mediatek.c             | 4 +---
 drivers/pci/controller/pcie-rockchip.c             | 5 ++---
 drivers/pci/controller/pcie-xilinx-nwl.c           | 7 +++----
 9 files changed, 16 insertions(+), 29 deletions(-)

Comments

Rob Herring June 1, 2020, 10:22 p.m. UTC | #1
On Mon, Jun 01, 2020 at 10:33:45PM +0800, Dejin Zheng wrote:
> Use devm_platform_ioremap_resource_byname() to simplify codes.
> it contains platform_get_resource_byname() and devm_ioremap_resource().
> 
> Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
>  drivers/pci/controller/pci-tegra.c                 | 8 +++-----
>  drivers/pci/controller/pci-xgene.c                 | 3 +--
>  drivers/pci/controller/pcie-altera-msi.c           | 3 +--
>  drivers/pci/controller/pcie-altera.c               | 9 +++------
>  drivers/pci/controller/pcie-mediatek.c             | 4 +---
>  drivers/pci/controller/pcie-rockchip.c             | 5 ++---
>  drivers/pci/controller/pcie-xilinx-nwl.c           | 7 +++----
>  9 files changed, 16 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index 1c15c8352125..74ffa03fde5f 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
>  
>  	pcie->is_rc = false;
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> -	pcie->reg_base = devm_ioremap_resource(dev, res);
> +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
>  	if (IS_ERR(pcie->reg_base)) {
>  		dev_err(dev, "missing \"reg\"\n");
>  		return PTR_ERR(pcie->reg_base);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 8c2543f28ba0..dcc460a54875 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
>  	rc->device_id = 0xffff;
>  	of_property_read_u32(np, "device-id", &rc->device_id);
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> -	pcie->reg_base = devm_ioremap_resource(dev, res);
> +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
>  	if (IS_ERR(pcie->reg_base)) {
>  		dev_err(dev, "missing \"reg\"\n");
>  		return PTR_ERR(pcie->reg_base);
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index e3e917243e10..3e608383df66 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>  {
>  	struct device *dev = pcie->dev;
>  	struct platform_device *pdev = to_platform_device(dev);
> -	struct resource *pads, *afi, *res;
> +	struct resource *res;
>  	const struct tegra_pcie_soc *soc = pcie->soc;
>  	int err;
>  
> @@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
>  		}
>  	}
>  
> -	pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
> -	pcie->pads = devm_ioremap_resource(dev, pads);
> +	pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
>  	if (IS_ERR(pcie->pads)) {
>  		err = PTR_ERR(pcie->pads);
>  		goto phys_put;
>  	}
>  
> -	afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
> -	pcie->afi = devm_ioremap_resource(dev, afi);
> +	pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
>  	if (IS_ERR(pcie->afi)) {
>  		err = PTR_ERR(pcie->afi);
>  		goto phys_put;
> diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> index d1efa8ffbae1..1431a18eb02c 100644
> --- a/drivers/pci/controller/pci-xgene.c
> +++ b/drivers/pci/controller/pci-xgene.c
> @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
>  	if (IS_ERR(port->csr_base))
>  		return PTR_ERR(port->csr_base);
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> -	port->cfg_base = devm_ioremap_resource(dev, res);
> +	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
>  	if (IS_ERR(port->cfg_base))
>  		return PTR_ERR(port->cfg_base);
>  	port->cfg_addr = res->start;
> diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
> index 16d938920ca5..613e19af71bd 100644
> --- a/drivers/pci/controller/pcie-altera-msi.c
> +++ b/drivers/pci/controller/pcie-altera-msi.c
> @@ -228,8 +228,7 @@ static int altera_msi_probe(struct platform_device *pdev)
>  	mutex_init(&msi->lock);
>  	msi->pdev = pdev;
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
> -	msi->csr_base = devm_ioremap_resource(&pdev->dev, res);
> +	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
>  	if (IS_ERR(msi->csr_base)) {
>  		dev_err(&pdev->dev, "failed to map csr memory\n");
>  		return PTR_ERR(msi->csr_base);
> diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> index 24cb1c331058..7200e40ffa26 100644
> --- a/drivers/pci/controller/pcie-altera.c
> +++ b/drivers/pci/controller/pcie-altera.c
> @@ -696,17 +696,14 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
>  {
>  	struct device *dev = &pcie->pdev->dev;
>  	struct platform_device *pdev = pcie->pdev;
> -	struct resource *cra;
> -	struct resource *hip;
>  
> -	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
> -	pcie->cra_base = devm_ioremap_resource(dev, cra);
> +	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
>  	if (IS_ERR(pcie->cra_base))
>  		return PTR_ERR(pcie->cra_base);
>  
>  	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
> -		hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
> -		pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
> +		pcie->hip_base =
> +			devm_platform_ioremap_resource_byname(pdev, "Hip");
>  		if (IS_ERR(pcie->hip_base))
>  			return PTR_ERR(pcie->hip_base);
>  	}
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index ebfa7d5a4e2d..d8e38276dbe3 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -905,7 +905,6 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
>  			       int slot)
>  {
>  	struct mtk_pcie_port *port;
> -	struct resource *regs;
>  	struct device *dev = pcie->dev;
>  	struct platform_device *pdev = to_platform_device(dev);
>  	char name[10];
> @@ -916,8 +915,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
>  		return -ENOMEM;
>  
>  	snprintf(name, sizeof(name), "port%d", slot);
> -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> -	port->base = devm_ioremap_resource(dev, regs);
> +	port->base = devm_platform_ioremap_resource_byname(pdev, name);
>  	if (IS_ERR(port->base)) {
>  		dev_err(dev, "failed to map port%d base\n", slot);
>  		return PTR_ERR(port->base);
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index c53d1322a3d6..904dec0d3a88 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
> @@ -45,9 +45,8 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>  			return -EINVAL;
>  	}
>  
> -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -					    "apb-base");
> -	rockchip->apb_base = devm_ioremap_resource(dev, regs);
> +	rockchip->apb_base =
> +		devm_platform_ioremap_resource_byname(pdev, "apb-base");
>  	if (IS_ERR(rockchip->apb_base))
>  		return PTR_ERR(rockchip->apb_base);
>  
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
> index 9bd1427f2fd6..06d5ca33d008 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -777,14 +777,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
>  	struct device *dev = pcie->dev;
>  	struct resource *res;
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
> -	pcie->breg_base = devm_ioremap_resource(dev, res);
> +	pcie->breg_base = devm_platform_ioremap_resource_byname(pdev, "breg");
>  	if (IS_ERR(pcie->breg_base))
>  		return PTR_ERR(pcie->breg_base);
>  	pcie->phys_breg_base = res->start;
>  
> -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
> -	pcie->pcireg_base = devm_ioremap_resource(dev, res);
> +	pcie->pcireg_base =
> +		devm_platform_ioremap_resource_byname(pdev, "pcireg");
>  	if (IS_ERR(pcie->pcireg_base))
>  		return PTR_ERR(pcie->pcireg_base);
>  	pcie->phys_pcie_reg_base = res->start;

As 0-day pointed out, this hunk should be dropped as the phys address is 
needed.

Rob
Dejin Zheng June 2, 2020, 4:41 p.m. UTC | #2
On Tue, Jun 02, 2020 at 02:13:23AM +0800, kbuild test robot wrote:
> Hi Dejin,
> 
> Thank you for the patch! Perhaps something to improve:
>
Yes, you are right, I should not modify this file drivers/pci/controller/pcie-xilinx-nwl.c.
I will sent the patch v2. Thanks very much!

BR,
Dejin

> [auto build test WARNING on pci/next]
> [also build test WARNING on tegra/for-next rockchip/for-next v5.7 next-20200529]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system. BTW, we also suggest to use '--base' option to specify the
> base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
> 
> url:    https://github.com/0day-ci/linux/commits/Dejin-Zheng/PCI-controller-convert-to-devm_platform_ioremap_resource_byname/20200601-223757
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
> config: x86_64-allyesconfig (attached as .config)
> compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 2388a096e7865c043e83ece4e26654bd3d1a20d5)
> reproduce (this is a W=1 build):
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install x86_64 cross compiling tool for clang build
>         # apt-get install binutils-x86-64-linux-gnu
>         # save the attached .config to linux build tree
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kbuild test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>, old ones prefixed by <<):
> 
> >> drivers/pci/controller/pcie-xilinx-nwl.c:783:25: warning: variable 'res' is uninitialized when used here [-Wuninitialized]
> pcie->phys_breg_base = res->start;
> ^~~
> drivers/pci/controller/pcie-xilinx-nwl.c:778:22: note: initialize the variable 'res' to silence this warning
> struct resource *res;
> ^
> = NULL
> 1 warning generated.
> 
> vim +/res +783 drivers/pci/controller/pcie-xilinx-nwl.c
> 
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  773  
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  774  static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  775  			     struct platform_device *pdev)
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  776  {
> adf9e284b4f76d drivers/pci/host/pcie-xilinx-nwl.c       Bjorn Helgaas       2016-10-06  777  	struct device *dev = pcie->dev;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  778  	struct resource *res;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  779  
> 213cf573e1a8b2 drivers/pci/controller/pcie-xilinx-nwl.c Dejin Zheng         2020-06-01  780  	pcie->breg_base = devm_platform_ioremap_resource_byname(pdev, "breg");
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  781  	if (IS_ERR(pcie->breg_base))
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  782  		return PTR_ERR(pcie->breg_base);
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06 @783  	pcie->phys_breg_base = res->start;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  784  
> 213cf573e1a8b2 drivers/pci/controller/pcie-xilinx-nwl.c Dejin Zheng         2020-06-01  785  	pcie->pcireg_base =
> 213cf573e1a8b2 drivers/pci/controller/pcie-xilinx-nwl.c Dejin Zheng         2020-06-01  786  		devm_platform_ioremap_resource_byname(pdev, "pcireg");
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  787  	if (IS_ERR(pcie->pcireg_base))
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  788  		return PTR_ERR(pcie->pcireg_base);
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  789  	pcie->phys_pcie_reg_base = res->start;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  790  
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  791  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> cd00f084ed1d50 drivers/pci/host/pcie-xilinx-nwl.c       Lorenzo Pieralisi   2017-04-19  792  	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  793  	if (IS_ERR(pcie->ecam_base))
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  794  		return PTR_ERR(pcie->ecam_base);
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  795  	pcie->phys_ecam_base = res->start;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  796  
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  797  	/* Get intx IRQ number */
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  798  	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  799  	if (pcie->irq_intx < 0) {
> adf9e284b4f76d drivers/pci/host/pcie-xilinx-nwl.c       Bjorn Helgaas       2016-10-06  800  		dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
> 5fd4bf6a659e45 drivers/pci/host/pcie-xilinx-nwl.c       Fabio Estevam       2017-08-31  801  		return pcie->irq_intx;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  802  	}
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  803  
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  804  	irq_set_chained_handler_and_data(pcie->irq_intx,
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  805  					 nwl_pcie_leg_handler, pcie);
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  806  
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  807  	return 0;
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  808  }
> ab597d35ef11d2 drivers/pci/host/pcie-xilinx-nwl.c       Bharat Kumar Gogada 2016-03-06  809  
> 
> :::::: The code at line 783 was first introduced by commit
> :::::: ab597d35ef11d2a921e0ec507a9b7861bcb44cbd PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller
> 
> :::::: TO: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> :::::: CC: Bjorn Helgaas <bhelgaas@google.com>
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Dejin Zheng June 2, 2020, 4:58 p.m. UTC | #3
On Mon, Jun 01, 2020 at 04:22:29PM -0600, Rob Herring wrote:
> On Mon, Jun 01, 2020 at 10:33:45PM +0800, Dejin Zheng wrote:
> > Use devm_platform_ioremap_resource_byname() to simplify codes.
> > it contains platform_get_resource_byname() and devm_ioremap_resource().
> > 
> > Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com>
> > ---
> >  drivers/pci/controller/cadence/pcie-cadence-ep.c   | 3 +--
> >  drivers/pci/controller/cadence/pcie-cadence-host.c | 3 +--
> >  drivers/pci/controller/pci-tegra.c                 | 8 +++-----
> >  drivers/pci/controller/pci-xgene.c                 | 3 +--
> >  drivers/pci/controller/pcie-altera-msi.c           | 3 +--
> >  drivers/pci/controller/pcie-altera.c               | 9 +++------
> >  drivers/pci/controller/pcie-mediatek.c             | 4 +---
> >  drivers/pci/controller/pcie-rockchip.c             | 5 ++---
> >  drivers/pci/controller/pcie-xilinx-nwl.c           | 7 +++----
> >  9 files changed, 16 insertions(+), 29 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > index 1c15c8352125..74ffa03fde5f 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > @@ -408,8 +408,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
> >  
> >  	pcie->is_rc = false;
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> > -	pcie->reg_base = devm_ioremap_resource(dev, res);
> > +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> >  	if (IS_ERR(pcie->reg_base)) {
> >  		dev_err(dev, "missing \"reg\"\n");
> >  		return PTR_ERR(pcie->reg_base);
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index 8c2543f28ba0..dcc460a54875 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -225,8 +225,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> >  	rc->device_id = 0xffff;
> >  	of_property_read_u32(np, "device-id", &rc->device_id);
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> > -	pcie->reg_base = devm_ioremap_resource(dev, res);
> > +	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
> >  	if (IS_ERR(pcie->reg_base)) {
> >  		dev_err(dev, "missing \"reg\"\n");
> >  		return PTR_ERR(pcie->reg_base);
> > diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> > index e3e917243e10..3e608383df66 100644
> > --- a/drivers/pci/controller/pci-tegra.c
> > +++ b/drivers/pci/controller/pci-tegra.c
> > @@ -1462,7 +1462,7 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
> >  {
> >  	struct device *dev = pcie->dev;
> >  	struct platform_device *pdev = to_platform_device(dev);
> > -	struct resource *pads, *afi, *res;
> > +	struct resource *res;
> >  	const struct tegra_pcie_soc *soc = pcie->soc;
> >  	int err;
> >  
> > @@ -1486,15 +1486,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
> >  		}
> >  	}
> >  
> > -	pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
> > -	pcie->pads = devm_ioremap_resource(dev, pads);
> > +	pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
> >  	if (IS_ERR(pcie->pads)) {
> >  		err = PTR_ERR(pcie->pads);
> >  		goto phys_put;
> >  	}
> >  
> > -	afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
> > -	pcie->afi = devm_ioremap_resource(dev, afi);
> > +	pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
> >  	if (IS_ERR(pcie->afi)) {
> >  		err = PTR_ERR(pcie->afi);
> >  		goto phys_put;
> > diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> > index d1efa8ffbae1..1431a18eb02c 100644
> > --- a/drivers/pci/controller/pci-xgene.c
> > +++ b/drivers/pci/controller/pci-xgene.c
> > @@ -355,8 +355,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
> >  	if (IS_ERR(port->csr_base))
> >  		return PTR_ERR(port->csr_base);
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
> > -	port->cfg_base = devm_ioremap_resource(dev, res);
> > +	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
> >  	if (IS_ERR(port->cfg_base))
> >  		return PTR_ERR(port->cfg_base);
> >  	port->cfg_addr = res->start;
> > diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
> > index 16d938920ca5..613e19af71bd 100644
> > --- a/drivers/pci/controller/pcie-altera-msi.c
> > +++ b/drivers/pci/controller/pcie-altera-msi.c
> > @@ -228,8 +228,7 @@ static int altera_msi_probe(struct platform_device *pdev)
> >  	mutex_init(&msi->lock);
> >  	msi->pdev = pdev;
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
> > -	msi->csr_base = devm_ioremap_resource(&pdev->dev, res);
> > +	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
> >  	if (IS_ERR(msi->csr_base)) {
> >  		dev_err(&pdev->dev, "failed to map csr memory\n");
> >  		return PTR_ERR(msi->csr_base);
> > diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> > index 24cb1c331058..7200e40ffa26 100644
> > --- a/drivers/pci/controller/pcie-altera.c
> > +++ b/drivers/pci/controller/pcie-altera.c
> > @@ -696,17 +696,14 @@ static int altera_pcie_parse_dt(struct altera_pcie *pcie)
> >  {
> >  	struct device *dev = &pcie->pdev->dev;
> >  	struct platform_device *pdev = pcie->pdev;
> > -	struct resource *cra;
> > -	struct resource *hip;
> >  
> > -	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
> > -	pcie->cra_base = devm_ioremap_resource(dev, cra);
> > +	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
> >  	if (IS_ERR(pcie->cra_base))
> >  		return PTR_ERR(pcie->cra_base);
> >  
> >  	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
> > -		hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
> > -		pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
> > +		pcie->hip_base =
> > +			devm_platform_ioremap_resource_byname(pdev, "Hip");
> >  		if (IS_ERR(pcie->hip_base))
> >  			return PTR_ERR(pcie->hip_base);
> >  	}
> > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > index ebfa7d5a4e2d..d8e38276dbe3 100644
> > --- a/drivers/pci/controller/pcie-mediatek.c
> > +++ b/drivers/pci/controller/pcie-mediatek.c
> > @@ -905,7 +905,6 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> >  			       int slot)
> >  {
> >  	struct mtk_pcie_port *port;
> > -	struct resource *regs;
> >  	struct device *dev = pcie->dev;
> >  	struct platform_device *pdev = to_platform_device(dev);
> >  	char name[10];
> > @@ -916,8 +915,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
> >  		return -ENOMEM;
> >  
> >  	snprintf(name, sizeof(name), "port%d", slot);
> > -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
> > -	port->base = devm_ioremap_resource(dev, regs);
> > +	port->base = devm_platform_ioremap_resource_byname(pdev, name);
> >  	if (IS_ERR(port->base)) {
> >  		dev_err(dev, "failed to map port%d base\n", slot);
> >  		return PTR_ERR(port->base);
> > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> > index c53d1322a3d6..904dec0d3a88 100644
> > --- a/drivers/pci/controller/pcie-rockchip.c
> > +++ b/drivers/pci/controller/pcie-rockchip.c
> > @@ -45,9 +45,8 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
> >  			return -EINVAL;
> >  	}
> >  
> > -	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > -					    "apb-base");
> > -	rockchip->apb_base = devm_ioremap_resource(dev, regs);
> > +	rockchip->apb_base =
> > +		devm_platform_ioremap_resource_byname(pdev, "apb-base");
> >  	if (IS_ERR(rockchip->apb_base))
> >  		return PTR_ERR(rockchip->apb_base);
> >  
> > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
> > index 9bd1427f2fd6..06d5ca33d008 100644
> > --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> > @@ -777,14 +777,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
> >  	struct device *dev = pcie->dev;
> >  	struct resource *res;
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
> > -	pcie->breg_base = devm_ioremap_resource(dev, res);
> > +	pcie->breg_base = devm_platform_ioremap_resource_byname(pdev, "breg");
> >  	if (IS_ERR(pcie->breg_base))
> >  		return PTR_ERR(pcie->breg_base);
> >  	pcie->phys_breg_base = res->start;
> >  
> > -	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
> > -	pcie->pcireg_base = devm_ioremap_resource(dev, res);
> > +	pcie->pcireg_base =
> > +		devm_platform_ioremap_resource_byname(pdev, "pcireg");
> >  	if (IS_ERR(pcie->pcireg_base))
> >  		return PTR_ERR(pcie->pcireg_base);
> >  	pcie->phys_pcie_reg_base = res->start;
> 
> As 0-day pointed out, this hunk should be dropped as the phys address is 
> needed.
>
Rob, You are right, Sincerely thank you for helping me! I will sent the
patch v2.

BR,
Dejin
> Rob
diff mbox series

Patch

diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 1c15c8352125..74ffa03fde5f 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -408,8 +408,7 @@  int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 
 	pcie->is_rc = false;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
-	pcie->reg_base = devm_ioremap_resource(dev, res);
+	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
 	if (IS_ERR(pcie->reg_base)) {
 		dev_err(dev, "missing \"reg\"\n");
 		return PTR_ERR(pcie->reg_base);
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 8c2543f28ba0..dcc460a54875 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -225,8 +225,7 @@  int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	rc->device_id = 0xffff;
 	of_property_read_u32(np, "device-id", &rc->device_id);
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
-	pcie->reg_base = devm_ioremap_resource(dev, res);
+	pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
 	if (IS_ERR(pcie->reg_base)) {
 		dev_err(dev, "missing \"reg\"\n");
 		return PTR_ERR(pcie->reg_base);
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index e3e917243e10..3e608383df66 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1462,7 +1462,7 @@  static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
-	struct resource *pads, *afi, *res;
+	struct resource *res;
 	const struct tegra_pcie_soc *soc = pcie->soc;
 	int err;
 
@@ -1486,15 +1486,13 @@  static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 		}
 	}
 
-	pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
-	pcie->pads = devm_ioremap_resource(dev, pads);
+	pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
 	if (IS_ERR(pcie->pads)) {
 		err = PTR_ERR(pcie->pads);
 		goto phys_put;
 	}
 
-	afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
-	pcie->afi = devm_ioremap_resource(dev, afi);
+	pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
 	if (IS_ERR(pcie->afi)) {
 		err = PTR_ERR(pcie->afi);
 		goto phys_put;
diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
index d1efa8ffbae1..1431a18eb02c 100644
--- a/drivers/pci/controller/pci-xgene.c
+++ b/drivers/pci/controller/pci-xgene.c
@@ -355,8 +355,7 @@  static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
 	if (IS_ERR(port->csr_base))
 		return PTR_ERR(port->csr_base);
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
-	port->cfg_base = devm_ioremap_resource(dev, res);
+	port->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
 	if (IS_ERR(port->cfg_base))
 		return PTR_ERR(port->cfg_base);
 	port->cfg_addr = res->start;
diff --git a/drivers/pci/controller/pcie-altera-msi.c b/drivers/pci/controller/pcie-altera-msi.c
index 16d938920ca5..613e19af71bd 100644
--- a/drivers/pci/controller/pcie-altera-msi.c
+++ b/drivers/pci/controller/pcie-altera-msi.c
@@ -228,8 +228,7 @@  static int altera_msi_probe(struct platform_device *pdev)
 	mutex_init(&msi->lock);
 	msi->pdev = pdev;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
-	msi->csr_base = devm_ioremap_resource(&pdev->dev, res);
+	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
 	if (IS_ERR(msi->csr_base)) {
 		dev_err(&pdev->dev, "failed to map csr memory\n");
 		return PTR_ERR(msi->csr_base);
diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
index 24cb1c331058..7200e40ffa26 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -696,17 +696,14 @@  static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 {
 	struct device *dev = &pcie->pdev->dev;
 	struct platform_device *pdev = pcie->pdev;
-	struct resource *cra;
-	struct resource *hip;
 
-	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
-	pcie->cra_base = devm_ioremap_resource(dev, cra);
+	pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
 	if (IS_ERR(pcie->cra_base))
 		return PTR_ERR(pcie->cra_base);
 
 	if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
-		hip = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Hip");
-		pcie->hip_base = devm_ioremap_resource(&pdev->dev, hip);
+		pcie->hip_base =
+			devm_platform_ioremap_resource_byname(pdev, "Hip");
 		if (IS_ERR(pcie->hip_base))
 			return PTR_ERR(pcie->hip_base);
 	}
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index ebfa7d5a4e2d..d8e38276dbe3 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -905,7 +905,6 @@  static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
 			       int slot)
 {
 	struct mtk_pcie_port *port;
-	struct resource *regs;
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	char name[10];
@@ -916,8 +915,7 @@  static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
 		return -ENOMEM;
 
 	snprintf(name, sizeof(name), "port%d", slot);
-	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
-	port->base = devm_ioremap_resource(dev, regs);
+	port->base = devm_platform_ioremap_resource_byname(pdev, name);
 	if (IS_ERR(port->base)) {
 		dev_err(dev, "failed to map port%d base\n", slot);
 		return PTR_ERR(port->base);
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
index c53d1322a3d6..904dec0d3a88 100644
--- a/drivers/pci/controller/pcie-rockchip.c
+++ b/drivers/pci/controller/pcie-rockchip.c
@@ -45,9 +45,8 @@  int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
 			return -EINVAL;
 	}
 
-	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-					    "apb-base");
-	rockchip->apb_base = devm_ioremap_resource(dev, regs);
+	rockchip->apb_base =
+		devm_platform_ioremap_resource_byname(pdev, "apb-base");
 	if (IS_ERR(rockchip->apb_base))
 		return PTR_ERR(rockchip->apb_base);
 
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 9bd1427f2fd6..06d5ca33d008 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -777,14 +777,13 @@  static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
 	struct device *dev = pcie->dev;
 	struct resource *res;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
-	pcie->breg_base = devm_ioremap_resource(dev, res);
+	pcie->breg_base = devm_platform_ioremap_resource_byname(pdev, "breg");
 	if (IS_ERR(pcie->breg_base))
 		return PTR_ERR(pcie->breg_base);
 	pcie->phys_breg_base = res->start;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
-	pcie->pcireg_base = devm_ioremap_resource(dev, res);
+	pcie->pcireg_base =
+		devm_platform_ioremap_resource_byname(pdev, "pcireg");
 	if (IS_ERR(pcie->pcireg_base))
 		return PTR_ERR(pcie->pcireg_base);
 	pcie->phys_pcie_reg_base = res->start;