| Message ID | 20191208210320.15539-2-repk@triplefau.lt |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: amlogic: Make PCIe working reliably on AXG platforms | expand |
Hi Remi, On Sun, Dec 8, 2019 at 9:56 PM Remi Pommarel <repk@triplefau.lt> wrote: [...] > +static MESON_GATE(axg_pcie_pll_cml_enable, HHI_MIPI_CNTL0, 26); we already have CLKID_PCIE_CML_EN0 do you know how this new one is related (in terms of clock hierarchy) to the existing one? [...] > --- a/include/dt-bindings/clock/axg-clkc.h > +++ b/include/dt-bindings/clock/axg-clkc.h > @@ -72,5 +72,6 @@ > #define CLKID_PCIE_CML_EN1 80 > #define CLKID_MIPI_ENABLE 81 > #define CLKID_GEN_CLK 84 > +#define CLKID_PCIE_PLL_CML_ENABLE 91 this has to be a separate patch if you want the .dts patch to go into the same cycle the .dts change depends on this one. what we typically do is to apply the dt-bindings patches to a separate clock branch, create an immutable tag and then Kevin pulls that into his dt64 branch. the clock controller changes go into a separate patch in the clk-meson/drivers branch to avoid conflicts with other driver changes Martin
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 13fc0006f63d..ac9ab7f75ee8 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1142,6 +1142,7 @@ static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29); +static MESON_GATE(axg_pcie_pll_cml_enable, HHI_MIPI_CNTL0, 26); /* Always On (AO) domain gates */ @@ -1246,6 +1247,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, + [CLKID_PCIE_PLL_CML_ENABLE] = &axg_pcie_pll_cml_enable.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -1341,6 +1343,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_hifi_pll_dco, &axg_pcie_pll_dco, &axg_pcie_pll_od, + &axg_pcie_pll_cml_enable, }; static const struct meson_eeclkc_data axg_clkc_data = { diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 0431dabac629..d65670d6c607 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -140,7 +140,7 @@ #define CLKID_PCIE_PLL_DCO 89 #define CLKID_PCIE_PLL_OD 90 -#define NR_CLKS 91 +#define NR_CLKS 92 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index fd1f938c38d1..218a05ff508d 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -72,5 +72,6 @@ #define CLKID_PCIE_CML_EN1 80 #define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 +#define CLKID_PCIE_PLL_CML_ENABLE 91 #endif /* __AXG_CLKC_H */
PCIE_PLL_CML_ENABLE is used to enable or disable pcie clock PAD output reliably on AXG platforms. Signed-off-by: Remi Pommarel <repk@triplefau.lt> --- drivers/clk/meson/axg.c | 3 +++ drivers/clk/meson/axg.h | 2 +- include/dt-bindings/clock/axg-clkc.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-)