diff mbox series

[v4,3/3] PCI/ACPI: Refactor _OSC request bit setting

Message ID 20190701204515.23374-4-asierra@xes-inc.com
State Changes Requested
Delegated to: Bjorn Helgaas
Headers show
Series Improve _OSC control request granularity | expand

Commit Message

Aaron Sierra July 1, 2019, 8:45 p.m. UTC 
Provide an inline function for each feature (ASPM, PCIe hotplug, SHPC
hotplug, and AER) to set its _OSC requests after performing any
sanity checks that it needs. This is intended to improve
readability/maintenance.

Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
---
 drivers/acpi/pci_root.c | 75 ++++++++++++++++++++++++++++++-----------
 1 file changed, 55 insertions(+), 20 deletions(-)
diff mbox series

Patch

diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 9b8a44391ea0..4e499bb23352 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -431,6 +431,54 @@  static inline bool osc_have_support(u32 support, u32 required)
 	return ((support & required) == required);
 }
 
+static inline u32 osc_get_aspm_control_bits(struct acpi_pci_root *root,
+					    u32 support)
+{
+	if (osc_have_support(support, ACPI_PCIE_ASPM_SUPPORT))
+		return OSC_CONTROL_BITS_ASPM;
+
+	return 0;
+}
+
+static inline u32 osc_get_pciehp_control_bits(struct acpi_pci_root *root,
+					      u32 support)
+{
+	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE) &&
+	    osc_have_support(support, ACPI_PCIE_REQ_SUPPORT)) {
+		return OSC_PCI_EXPRESS_CAPABILITY_CONTROL |
+		       OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
+	}
+
+	return 0;
+}
+
+static inline u32 osc_get_shpchp_control_bits(struct acpi_pci_root *root,
+					      u32 support)
+{
+	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC) &&
+	    osc_have_support(support, ACPI_PCIE_REQ_SUPPORT)) {
+		return OSC_PCI_EXPRESS_CAPABILITY_CONTROL |
+		       OSC_PCI_SHPC_NATIVE_HP_CONTROL;
+	}
+
+	return 0;
+}
+
+static inline u32 osc_get_aer_control_bits(struct acpi_pci_root *root,
+					   u32 support)
+{
+	if (!pci_aer_available() ||
+	    !osc_have_support(support, ACPI_PCIE_REQ_SUPPORT))
+		return 0;
+
+	if (aer_acpi_firmware_first()) {
+		dev_info(&root->device->dev, "PCIe AER handled by firmware\n");
+		return 0;
+	}
+
+	return OSC_PCI_EXPRESS_CAPABILITY_CONTROL | OSC_PCI_EXPRESS_AER_CONTROL;
+}
+
 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 				 bool is_pcie)
 {
@@ -494,29 +542,16 @@  static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 		return;
 	}
 
-	control = 0;
-
-	if (osc_have_support(support, ACPI_PCIE_ASPM_SUPPORT))
-		control |= OSC_CONTROL_BITS_ASPM;
-
+	control = osc_get_aspm_control_bits(root, support);
 	if (!control)
 		*no_aspm = 1;
 
-	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
-		control |= OSC_PCI_EXPRESS_CAPABILITY_CONTROL |
-			   OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
-
-	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
-		control |= OSC_PCI_EXPRESS_CAPABILITY_CONTROL |
-			   OSC_PCI_SHPC_NATIVE_HP_CONTROL;
-
-	if (pci_aer_available()) {
-		if (aer_acpi_firmware_first())
-			dev_info(&device->dev,
-				 "PCIe AER handled by firmware\n");
-		else
-			control |= OSC_PCI_EXPRESS_CAPABILITY_CONTROL |
-				   OSC_PCI_EXPRESS_AER_CONTROL;
+	control |= osc_get_pciehp_control_bits(root, support);
+	control |= osc_get_shpchp_control_bits(root, support);
+	control |= osc_get_aer_control_bits(root, support);
+	if (!control) {
+		dev_info(&device->dev, "_OSC: not requesting OS control\n");
+		return;
 	}
 
 	requested = control;