From patchwork Thu Apr 11 17:03:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 1084218 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="W++Lmiqj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44g6qy0WvYz9s71 for ; Fri, 12 Apr 2019 03:06:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726931AbfDKRGV (ORCPT ); Thu, 11 Apr 2019 13:06:21 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7245 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726391AbfDKRGU (ORCPT ); Thu, 11 Apr 2019 13:06:20 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 11 Apr 2019 10:06:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:06:20 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 11 Apr 2019 10:06:20 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:06:19 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:06:19 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:06:16 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH 28/30] dt-bindings: pci: tegra: Document nvidia, rst-gpio optional prop Date: Thu, 11 Apr 2019 22:33:53 +0530 Message-ID: <20190411170355.6882-29-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002377; bh=wQ7UEUDOdwq/fRnKEQzSHuLOlmEe/J5abtWcbK20KxQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=W++LmiqjGI3fkrChzCgiZT7P0CKbScL5ZtmtH9PvEw026w2LwuaGQ6sTiroyjjR/3 sKpd2zHTAB9MwGHzAT95/vWAOTZaVhwt1zdCN5fs+Cp+yjpmLksZpYAyOUJ0XiSYKn f6LI+33rdILws5Ia4nlQKkt+QiHgrYsArQ0iJi7qat6csUgMLfyuFRU1ANCYZqccvy WCeqVxmJfgeoADRbFOH8r0RPplXI7O+pRQAr6nrTe6bfUzZSqAfcNoYiirzQFQ61Gy UPDmqBw7O5QwME38j7Jz+IyBVrQSA+h2oCCajEA138t4/JzH7bLrYrMCg1rNTyH6T2 zr5ufhuED2IjA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document "nvidia,rst-gpio" optional property which supports GPIO based PERST# signal. Signed-off-by: Manikanta Maddireddy --- Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index dca8393b86d1..23928fd59538 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -75,6 +75,8 @@ Optional properties: Pass pinctrl phandle to allow driver bring PCIe IO out of DPD state. - nvidia,plat-gpios: A list of platform specific gpios which controls endpoint's internal regulator or PCIe logic. +- nvidia,rst-gpio: If GPIO is used as PERST# signal instead of available + SFIO, add this property with phandle to GPIO controller and GPIO number. Required properties on Tegra124 and later (deprecated): - phys: Must contain an entry for each entry in phy-names. @@ -671,6 +673,7 @@ Board DTS: pci@1,0 { nvidia,num-lanes = <4>; + nvidia,rst-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(A, 3) 0>; status = "okay"; };