From patchwork Tue Jun 20 01:33:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Axtens X-Patchwork-Id: 778054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ws9NY5cTtz9s4s for ; Tue, 20 Jun 2017 11:33:49 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=axtens.net header.i=@axtens.net header.b="HtExsXiI"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751019AbdFTBds (ORCPT ); Mon, 19 Jun 2017 21:33:48 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:35896 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750999AbdFTBdr (ORCPT ); Mon, 19 Jun 2017 21:33:47 -0400 Received: by mail-pf0-f195.google.com with SMTP id y7so20165735pfd.3 for ; Mon, 19 Jun 2017 18:33:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axtens.net; s=google; h=from:to:cc:subject:date:message-id; bh=65JqemgBMnOTbRm3X14M5kzWhTVisFygs+Jvan8WNI0=; b=HtExsXiI9o7VobjDItG9k5Yq4701s17zyE98AJC0XMZtuzO9sV51cmFFHq6lUeUpgZ 2dimAq8nRy3Ma7dTPucmTSL6UEl72EhxipwkxpujUTgvH/r/yFNe8IahitgYMoTyoYZi wWaHugjrUpuaq5db+hUqmDxJFtpTGdQaM+SLY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=65JqemgBMnOTbRm3X14M5kzWhTVisFygs+Jvan8WNI0=; b=ITkl3JeXT9gZJcOrm7VPx78UzQxK6lZkH2CiTfi8D+flNBWdwfjxu7ryLJuM0H0IEZ qH/44jkwSxC4iHDh9Y9NTA+CJ8OlHjY7Z0oazLot78P1KVQvS8feBLDD+X9ZvsEVdyCb d2zijK0Oh+cCk5ZXT7RrPZfAqh56zl9v7JonkYZoQ5b8O2r5N/hZqT3qou+cBPCgkUQ4 OjE6M6m94OAv3bV/h7zH81kLi11T2XQlIJ8oecokygmuQhES7iGlh4Cq0H6GsMjYxWrL eKLTIsOy9sC6uB13mxIuJOuaprUxsT331mbXc3toMso9RapLe3unYu80UAyKJu37fh5n 3UoQ== X-Gm-Message-State: AKS2vOw4xdTyvCfN9xnZyTNRnXYw0Wl0gYJzw3KUlqP06gGorGC5ysru Cm3gU47jCXvxBkIeWA/JLw== X-Received: by 10.84.215.212 with SMTP id g20mr14914141plj.124.1497922426993; Mon, 19 Jun 2017 18:33:46 -0700 (PDT) Received: from localhost.localdomain (us.sesame.canonical.com. [91.189.91.19]) by smtp.gmail.com with ESMTPSA id s88sm24229019pfk.16.2017.06.19.18.33.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Jun 2017 18:33:46 -0700 (PDT) From: Daniel Axtens To: linux-pci@vger.kernel.org Cc: Daniel Axtens , Xinliang Liu , Rongrong Zou Subject: [PATCH v2] PCI: Support hibmc VGA cards behind a misbehaving HiSilicon bridge Date: Tue, 20 Jun 2017 11:33:02 +1000 Message-Id: <20170620013302.528-1-dja@axtens.net> X-Mailer: git-send-email 2.11.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The HiSilicon D05 board has some PCI bridges (PCI ID 19e5:1610) that are not spec-compliant: the VGA Enable bit is set to 0 in hardware and writes do not change it. This stops VGA arbitrartion from marking a VGA card behind the bridge as a boot device, and therefore breaks Xorg auto-configuration. The hibmc VGA card (PCI ID 19e5:1711) is known to work when behind these bridges. Provide a quirk so that this combination of bridge and card is eligible to be the default VGA card. This fixes Xorg auto-detection. Cc: Xinliang Liu Cc: Rongrong Zou Signed-off-by: Daniel Axtens --- drivers/pci/quirks.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 16e6cd86ad71..86d7c848f3e2 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -25,6 +25,7 @@ #include #include #include +#include #include /* isa_dma_bridge_buggy */ #include "pci.h" @@ -4664,3 +4665,48 @@ static void quirk_intel_no_flr(struct pci_dev *dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); + +/* + * The hibmc card on a HiSilicon D05 board sits behind a non-compliant + * bridge. The bridge has the PCI_BRIDGE_CTL_VGA config bit fixed at 0 + * in hardware. This prevents the vgaarb from marking a card behind it + * as boot VGA device. + * + * However, the hibmc card is known to still work, so if we have that + * card behind that particular bridge (19e5:1610), mark it as the + * default device if none has been detected. + */ +static void hibmc_fixup_vgaarb(struct pci_dev *pdev) +{ + struct pci_dev *bridge; + struct pci_bus *bus; + u16 config; + + bus = pdev->bus; + bridge = bus->self; + if (!bridge) + return; + + if (!pci_is_bridge(bridge)) + return; + + if (bridge->vendor != PCI_VENDOR_ID_HUAWEI || + bridge->device != 0x1610) + return; + + pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, + &config); + if (config & PCI_BRIDGE_CTL_VGA) { + /* + * Weirdly, this bridge *is* spec compliant, so bail + * and let vgaarb do its job + */ + return; + } + + if (vga_default_device()) + return; + + vga_set_default_device(pdev); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1711, hibmc_fixup_vgaarb);