From patchwork Tue Apr 11 12:28:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 749443 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3w2RFj5Qd1z9sNV for ; Tue, 11 Apr 2017 22:29:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752187AbdDKM3j (ORCPT ); Tue, 11 Apr 2017 08:29:39 -0400 Received: from foss.arm.com ([217.140.101.70]:59778 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751514AbdDKM3j (ORCPT ); Tue, 11 Apr 2017 08:29:39 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E94E1688; Tue, 11 Apr 2017 05:29:38 -0700 (PDT) Received: from red-moon.cambridge.arm.com (red-moon.cambridge.arm.com [10.1.206.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 010343F23B; Tue, 11 Apr 2017 05:29:36 -0700 (PDT) From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Bjorn Helgaas , Richard Henderson , Ivan Kokshaysky , Matt Turner Subject: [PATCH v3 05/32] alpha: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 13:28:45 +0100 Message-Id: <20170411122923.6285-6-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Include the asm-generic ioremap_nopost() implementation (currently falling back to ioremap_nocache()) to provide a non-posted writes ioremap interface to kernel subsystems. Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Richard Henderson Cc: Ivan Kokshaysky Cc: Matt Turner --- arch/alpha/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index ff40491..5d7cc11 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -300,6 +300,7 @@ static inline void __iomem * ioremap_nocache(unsigned long offset, } #define ioremap_uc ioremap_nocache +#include static inline void iounmap(volatile void __iomem *addr) {