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[213.113.113.53]) by smtp.gmail.com with ESMTPSA id c65sm1276410ljd.44.2017.02.11.04.53.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 11 Feb 2017 04:53:04 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Rob Herring , devicetree@vger.kernel.org, Bjorn Helgaas , Gavin Guo , Macpaul Lin Cc: Janos Laube , Paulius Zaleckas , openwrt-devel@openwrt.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij , Feng-Hsin Chiang Subject: [PATCH 4/4] ARM: dts: add PCI to the Gemini device trees Date: Sat, 11 Feb 2017 13:52:20 +0100 Message-Id: <20170211125220.10273-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170211125220.10273-1-linus.walleij@linaro.org> References: <20170211125220.10273-1-linus.walleij@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Cortina Gemini has an internal PCI root bus, add this to the device tree, and add interrupt mapping (swizzling) to the relevant systems device trees. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Cc: Gavin Guo Cc: Macpaul Lin Cc: Feng-Hsin Chiang Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Change bus-range to <0x00 0xff> - Drop the three extra IRQs that are unused - Implement the right interrupt mapping/swizzling - Push the interrupt mapping down to each affected system, only SQ201 for now. PCI maintainers: this is FYI only, I will funnel this to the ARM SoC tree once we are done with the PCI driver. --- arch/arm/boot/dts/gemini-sq201.dts | 22 ++++++++++++++++++++++ arch/arm/boot/dts/gemini.dtsi | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index dae2a70d8fbc..46309e79cc7b 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -92,5 +92,27 @@ read-only; }; }; + + pci@50000000 { + status = "okay"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4800 0 0 2 &pci_intc 1>, + <0x4800 0 0 3 &pci_intc 2>, + <0x4800 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ + <0x5000 0 0 2 &pci_intc 2>, + <0x5000 0 0 3 &pci_intc 3>, + <0x5000 0 0 4 &pci_intc 0>, + <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ + <0x5800 0 0 2 &pci_intc 3>, + <0x5800 0 0 3 &pci_intc 0>, + <0x5800 0 0 4 &pci_intc 1>, + <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ + <0x6000 0 0 2 &pci_intc 0>, + <0x6000 0 0 3 &pci_intc 1>, + <0x6000 0 0 4 &pci_intc 2>; + }; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index ed2314a3a804..2eddc698795e 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -104,5 +104,37 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pci@50000000 { + compatible = "faraday,pci"; + /* + * The first 256 bytes in the IO range is actually used + * to configure the host bridge. + */ + reg = <0x50000000 0x100>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + status = "disabled"; + + bus-range = <0x00 0xff>; + /* PCI ranges mappings */ + ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + + /* + * This PCI host bridge variant has a cascaded interrupt + * controller embedded in the host bridge. + */ + pci_intc: interrupt-controller { + interrupt-parent = <&intcon>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; }; };