diff mbox

[08/11] PCI: hisi: Replace hisi_apb_readl() with dw_pcie_readl_rc()

Message ID 20161007163750.25540.95889.stgit@bhelgaas-glaptop2.roam.corp.google.com
State Not Applicable
Headers show

Commit Message

Bjorn Helgaas Oct. 7, 2016, 4:37 p.m. UTC 
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces do the same as
hisi_apb_readl() and hisi_apb_writel(), and they also give us a clue that
we're using the DesignWare-generic functionality.  Use the dw_*()
interfaces and remove the hisi-specific ones.  No functional change
intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 drivers/pci/host/pcie-hisi.c |   26 +++++++-------------------
 1 file changed, 7 insertions(+), 19 deletions(-)


--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff mbox

Patch

diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
index c6b0459..707dafd 100644
--- a/drivers/pci/host/pcie-hisi.c
+++ b/drivers/pci/host/pcie-hisi.c
@@ -43,27 +43,16 @@  struct hisi_pcie {
 	struct pcie_soc_ops *soc_ops;
 };
 
-static u32 hisi_apb_readl(struct hisi_pcie *hisi, u32 reg)
-{
-	return readl(hisi->pp.dbi_base + reg);
-}
-
-static void hisi_apb_writel(struct hisi_pcie *hisi, u32 reg, u32 val)
-{
-	writel(val, hisi->pp.dbi_base + reg);
-}
-
 /* HipXX PCIe host only supports 32-bit config access */
 static int hisi_cfg_read(struct pcie_port *pp, int where, int size, u32 *val)
 {
-	struct hisi_pcie *hisi = to_hisi_pcie(pp);
 	u32 reg;
 	u32 reg_val;
 	void *walker = &reg_val;
 
 	walker += (where & 0x3);
 	reg = where & ~0x3;
-	reg_val = hisi_apb_readl(hisi, reg);
+	reg_val = dw_pcie_readl_rc(pp, reg);
 
 	if (size == 1)
 		*val = *(u8 __force *) walker;
@@ -80,7 +69,6 @@  static int hisi_cfg_read(struct pcie_port *pp, int where, int size, u32 *val)
 /* HipXX PCIe host only supports 32-bit config access */
 static int hisi_cfg_write(struct pcie_port *pp, int where, int  size, u32 val)
 {
-	struct hisi_pcie *hisi = to_hisi_pcie(pp);
 	u32 reg_val;
 	u32 reg;
 	void *walker = &reg_val;
@@ -88,15 +76,15 @@  static int hisi_cfg_write(struct pcie_port *pp, int where, int  size, u32 val)
 	walker += (where & 0x3);
 	reg = where & ~0x3;
 	if (size == 4)
-		hisi_apb_writel(hisi, reg, val);
+		dw_pcie_writel_rc(pp, reg, val);
 	else if (size == 2) {
-		reg_val = hisi_apb_readl(hisi, reg);
+		reg_val = dw_pcie_readl_rc(pp, reg);
 		*(u16 __force *) walker = val;
-		hisi_apb_writel(hisi, reg, reg_val);
+		dw_pcie_writel_rc(pp, reg, reg_val);
 	} else if (size == 1) {
-		reg_val = hisi_apb_readl(hisi, reg);
+		reg_val = dw_pcie_readl_rc(pp, reg);
 		*(u8 __force *) walker = val;
-		hisi_apb_writel(hisi, reg, reg_val);
+		dw_pcie_writel_rc(pp, reg, reg_val);
 	} else
 		return PCIBIOS_BAD_REGISTER_NUMBER;
 
@@ -116,7 +104,7 @@  static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi)
 {
 	u32 val;
 
-	val = hisi_apb_readl(hisi, PCIE_HIP06_CTRL_OFF + PCIE_SYS_STATE4);
+	val = dw_pcie_readl_rc(&hisi->pp, PCIE_HIP06_CTRL_OFF + PCIE_SYS_STATE4);
 
 	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
 }