From patchwork Fri Oct 7 16:26:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 679515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3srFJt6wbFz9rxv for ; Sat, 8 Oct 2016 03:26:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938958AbcJGQ0h (ORCPT ); Fri, 7 Oct 2016 12:26:37 -0400 Received: from mail.kernel.org ([198.145.29.136]:48056 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938941AbcJGQ0h (ORCPT ); Fri, 7 Oct 2016 12:26:37 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7B87E20374; Fri, 7 Oct 2016 16:26:35 +0000 (UTC) Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 634332034B; Fri, 7 Oct 2016 16:26:34 +0000 (UTC) Subject: [PATCH 3/5] PCI: tegra: Swap order of pads_writel() reg/val arguments To: Alexandre Courbot , Thierry Reding , Stephen Warren From: Bjorn Helgaas Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Date: Fri, 07 Oct 2016 11:26:32 -0500 Message-ID: <20161007162632.23718.27618.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20161007162615.23718.84354.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20161007162615.23718.84354.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, NML_ADSP_CUSTOM_MED,UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Swap order of pads_writel() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas Acked-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 146b69f..4b01893 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -337,13 +337,13 @@ static u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) return readl(pcie->afi + offset); } -static inline void pads_writel(struct tegra_pcie *pcie, u32 value, - unsigned long offset) +static void pads_writel(struct tegra_pcie *pcie, unsigned long offset, + u32 value) { writel(value, pcie->pads + offset); } -static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) +static u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) { return readl(pcie->pads + offset); } @@ -797,12 +797,12 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) int err; /* initialize internal PHY, enable up to 16 PCIE lanes */ - pads_writel(pcie, 0x0, PADS_CTL_SEL); + pads_writel(pcie, PADS_CTL_SEL, 0); /* override IDDQ to 1 on all 4 lanes */ value = pads_readl(pcie, PADS_CTL); value |= PADS_CTL_IDDQ_1L; - pads_writel(pcie, value, PADS_CTL); + pads_writel(pcie, PADS_CTL, value); /* * Set up PHY PLL inputs select PLLE output as refclock, @@ -811,19 +811,19 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) value = pads_readl(pcie, soc->pads_pll_ctl); value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; - pads_writel(pcie, value, soc->pads_pll_ctl); + pads_writel(pcie, soc->pads_pll_ctl, value); /* reset PLL */ value = pads_readl(pcie, soc->pads_pll_ctl); value &= ~PADS_PLL_CTL_RST_B4SM; - pads_writel(pcie, value, soc->pads_pll_ctl); + pads_writel(pcie, soc->pads_pll_ctl, value); usleep_range(20, 100); /* take PLL out of reset */ value = pads_readl(pcie, soc->pads_pll_ctl); value |= PADS_PLL_CTL_RST_B4SM; - pads_writel(pcie, value, soc->pads_pll_ctl); + pads_writel(pcie, soc->pads_pll_ctl, value); /* wait for the PLL to lock */ err = tegra_pcie_pll_wait(pcie, 500); @@ -835,12 +835,12 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) /* turn off IDDQ override */ value = pads_readl(pcie, PADS_CTL); value &= ~PADS_CTL_IDDQ_1L; - pads_writel(pcie, value, PADS_CTL); + pads_writel(pcie, PADS_CTL, value); /* enable TX/RX data */ value = pads_readl(pcie, PADS_CTL); value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; - pads_writel(pcie, value, PADS_CTL); + pads_writel(pcie, PADS_CTL, value); return 0; } @@ -853,17 +853,17 @@ static int tegra_pcie_phy_disable(struct tegra_pcie *pcie) /* disable TX/RX data */ value = pads_readl(pcie, PADS_CTL); value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L); - pads_writel(pcie, value, PADS_CTL); + pads_writel(pcie, PADS_CTL, value); /* override IDDQ */ value = pads_readl(pcie, PADS_CTL); value |= PADS_CTL_IDDQ_1L; - pads_writel(pcie, value, PADS_CTL); + pads_writel(pcie, PADS_CTL, value); /* reset PLL */ value = pads_readl(pcie, soc->pads_pll_ctl); value &= ~PADS_PLL_CTL_RST_B4SM; - pads_writel(pcie, value, soc->pads_pll_ctl); + pads_writel(pcie, soc->pads_pll_ctl, value); usleep_range(20, 100); @@ -935,10 +935,10 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) } /* Configure the reference clock driver */ - pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); + pads_writel(pcie, PADS_REFCLK_CFG0, soc->pads_refclk_cfg0); if (soc->num_ports > 2) - pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); + pads_writel(pcie, PADS_REFCLK_CFG1, soc->pads_refclk_cfg1); return 0; }