diff mbox

[06/12] cxgb3: Use standard #defines for PCIe Capability ASPM fields

Message ID 20121205205750.13851.10893.stgit@bhelgaas.mtv.corp.google.com
State Accepted
Headers show

Commit Message

Bjorn Helgaas Dec. 5, 2012, 8:57 p.m. UTC
Use the standard #defines rather than bare numbers for PCIe Capability
ASPM fields.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Divy Le Ray <divy@chelsio.com>
CC: netdev@vger.kernel.org
---
 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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Comments

David Miller Dec. 7, 2012, 5:51 p.m. UTC | #1
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Wed, 05 Dec 2012 13:57:50 -0700

> Use the standard #defines rather than bare numbers for PCIe Capability
> ASPM fields.
> 
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

This seems to depend upon another patch which presumably adds the
define of this new macro to a PCI header file.  So I can't apply
this to my tree.

Just merge it wherever the dependency is:

Acked-by: David S. Miller <davem@davemloft.net>
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diff mbox

Patch

diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
index aef45d3..3dee686 100644
--- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
@@ -3307,7 +3307,7 @@  static void config_pcie(struct adapter *adap)
 	    G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
 	log2_width = fls(adap->params.pci.width) - 1;
 	acklat = ack_lat[log2_width][pldsize];
-	if (val & 1)		/* check LOsEnable */
+	if (val & PCI_EXP_LNKCTL_ASPM_L0S)	/* check LOsEnable */
 		acklat += fst_trn_tx * 4;
 	rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;