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Thu, 04 Apr 2024 19:11:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 434JBcUx026106 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 4 Apr 2024 19:11:38 GMT Received: from hu-mrana-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 4 Apr 2024 12:11:38 -0700 From: Mayank Rana To: , , , , , , , , , CC: , , , , , , Mayank Rana Subject: [RFC PATCH 1/2] dt-bindings: pcie: Document QCOM PCIE ECAM compatible root complex Date: Thu, 4 Apr 2024 12:11:23 -0700 Message-ID: <1712257884-23841-2-git-send-email-quic_mrana@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1712257884-23841-1-git-send-email-quic_mrana@quicinc.com> References: <1712257884-23841-1-git-send-email-quic_mrana@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nveXiKlpd99JpcAz8ILs6Hpg0n9Z5rxq X-Proofpoint-ORIG-GUID: nveXiKlpd99JpcAz8ILs6Hpg0n9Z5rxq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-04_15,2024-04-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404040136 On some of Qualcomm platform, firmware configures PCIe controller in RC mode with static iATU window mappings of configuration space for entire supported bus range in ECAM compatible mode. Firmware also manages PCIe PHY as well required system resources. Here document properties and required configuration to power up QCOM PCIe ECAM compatible root complex and PHY for PCIe functionality. Signed-off-by: Mayank Rana --- .../devicetree/bindings/pci/qcom,pcie-ecam.yaml | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml new file mode 100644 index 00000000..c209f12 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ecam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ECAM compliant PCI express root complex + +description: | + Qualcomm SOC based ECAM compatible PCIe root complex supporting MSI controller. + Firmware configures PCIe controller in RC mode with static iATU window mappings + of configuration space for entire supported bus range in ECAM compatible mode. + +maintainers: + - Mayank Rana + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/power-domain/power-domain-consumer.yaml + +properties: + compatible: + const: qcom,pcie-ecam-rc + + reg: + minItems: 1 + description: ECAM address space starting from root port till supported bus range + + interrupts: + minItems: 1 + maxItems: 8 + + ranges: + minItems: 2 + maxItems: 3 + + iommu-map: + minItems: 1 + maxItems: 16 + + power-domains: + maxItems: 1 + description: A phandle to node which is able support way to communicate with firmware + for enabling PCIe controller and PHY as well managing all system resources needed to + make both controller and PHY operational for PCIe functionality. + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - ranges + - power-domains + - device_type + - linux,pci-domain + - bus-range + +unevaluatedProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-ecam-rc"; + reg = <0x4 0x00000000 0 0x10000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40000000 0x0 0x40000000 0x0 0x100000>, + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x100000>; + bus-range = <0x00 0xff>; + dma-coherent; + linux,pci-domain = <0>; + power-domains = <&scmi5_pd 0>; + power-domain-names = "power"; + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + }; + }; +...