| Message ID | 1698729108-27356-5-git-send-email-quic_msarkar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: qcom: sa8775p: add support for EP PCIe | expand |
On Tue, Oct 31, 2023 at 10:41:48AM +0530, Mrinmay Sarkar wrote: > Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. > It supports gen4 and x2 link width. Limiting the speed to Gen3 due to > stability issues. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> One question below: > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 13dd44d..7eab458 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -3586,6 +3586,52 @@ > status = "disabled"; > }; > > + pcie0_ep: pcie-ep@1c00000 { > + compatible = "qcom,sa8775p-pcie-ep"; > + reg = <0x0 0x01c00000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf20>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x4000>, > + <0x0 0x40200000 0x0 0x100000>, > + <0x0 0x01c03000 0x0 0x1000>, > + <0x0 0x40005000 0x0 0x2000>; > + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > + "mmio", "dma"; > + > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; > + > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a"; > + > + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupt-names = "global", "doorbell", "dma"; > + > + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; > + interconnect-names = "pcie-mem", "cpu-pcie"; > + > + iommus = <&pcie_smmu 0x0000 0x7f>; SID is really 0? - Mani > + resets = <&gcc GCC_PCIE_0_BCR>; > + reset-names = "core"; > + power-domains = <&gcc PCIE_0_GDSC>; > + phys = <&pcie0_phy>; > + phy-names = "pciephy"; > + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ > + num-lanes = <2>; > + > + status = "disabled"; > + }; > + > pcie0_phy: phy@1c04000 { > compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; > reg = <0x0 0x1c04000 0x0 0x2000>; > -- > 2.7.4 >
On 11/1/2023 10:56 AM, Manivannan Sadhasivam wrote: > On Tue, Oct 31, 2023 at 10:41:48AM +0530, Mrinmay Sarkar wrote: >> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. >> It supports gen4 and x2 link width. Limiting the speed to Gen3 due to >> stability issues. >> >> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > One question below: > >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 13dd44d..7eab458 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -3586,6 +3586,52 @@ >> status = "disabled"; >> }; >> >> + pcie0_ep: pcie-ep@1c00000 { >> + compatible = "qcom,sa8775p-pcie-ep"; >> + reg = <0x0 0x01c00000 0x0 0x3000>, >> + <0x0 0x40000000 0x0 0xf20>, >> + <0x0 0x40000f20 0x0 0xa8>, >> + <0x0 0x40001000 0x0 0x4000>, >> + <0x0 0x40200000 0x0 0x100000>, >> + <0x0 0x01c03000 0x0 0x1000>, >> + <0x0 0x40005000 0x0 0x2000>; >> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", >> + "mmio", "dma"; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; >> + >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a"; >> + >> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; >> + >> + interrupt-names = "global", "doorbell", "dma"; >> + >> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; >> + interconnect-names = "pcie-mem", "cpu-pcie"; >> + >> + iommus = <&pcie_smmu 0x0000 0x7f>; > SID is really 0? > > - Mani Yes Mani, SA877P has SID 0x0 for pcie 0 controller and 0x80 for pcie 1 controller. > --Mrinmay > >> + resets = <&gcc GCC_PCIE_0_BCR>; >> + reset-names = "core"; >> + power-domains = <&gcc PCIE_0_GDSC>; >> + phys = <&pcie0_phy>; >> + phy-names = "pciephy"; >> + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ >> + num-lanes = <2>; >> + >> + status = "disabled"; >> + }; >> + >> pcie0_phy: phy@1c04000 { >> compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; >> reg = <0x0 0x1c04000 0x0 0x2000>; >> -- >> 2.7.4 >>
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 13dd44d..7eab458 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3586,6 +3586,52 @@ status = "disabled"; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>;
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)