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[V2] arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent

Message ID 1677584952-17496-1-git-send-email-quic_krichai@quicinc.com
State New
Headers show
Series [V2] arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent | expand

Commit Message

Krishna chaitanya chundru Feb. 28, 2023, 11:49 a.m. UTC
If the controller is not marked as cache coherent, then kernel will
try to ensure coherency during dma-ops and that may cause data corruption.
So, mark the PCIe node as dma-coherent as the devices on PCIe bus are
cache coherent.

Cc: stable@vger.kernel.org
Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related node")
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---

changes since v1:
	- Updated the commit text.
---
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++
 1 file changed, 2 insertions(+)

Comments

Bjorn Andersson March 7, 2023, 4:20 a.m. UTC | #1
On Tue, 28 Feb 2023 17:19:12 +0530, Krishna chaitanya chundru wrote:
> If the controller is not marked as cache coherent, then kernel will
> try to ensure coherency during dma-ops and that may cause data corruption.
> So, mark the PCIe node as dma-coherent as the devices on PCIe bus are
> cache coherent.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent
      commit: 8a63441e83724fee1ef3fd37b237d40d90780766

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index bdcb749..8f4ab6b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2131,6 +2131,8 @@ 
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_clkreq_n>;
 
+			dma-coherent;
+
 			iommus = <&apps_smmu 0x1c80 0x1>;
 
 			iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,