| Message ID | 1649294553-17310-2-git-send-email-hayashi.kunihiko@socionext.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: PCI: uniphier: Fix endpoint descriptions | expand |
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index e59059ab5be0..03f97e7c4089 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -28,11 +28,11 @@ properties: versions. For designware core version >= 4.80, it may contain ATU address space. minItems: 2 - maxItems: 4 + maxItems: 5 reg-names: minItems: 2 - maxItems: 4 + maxItems: 5 items: enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
UniPhier PCIe EP controller has up to 5 register mappings (dbi, dbi2, link, addr_space and atu), so maxItems of "reg" and "reg-names" should allow 5. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)