| Message ID | 1634237929-25459-1-git-send-email-pmaliset@codeaurora.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] PCI: qcom: Fix incorrect register offset in pcie init | expand |
This looks specific to SDM845, so the subject line should mention SDM845, e.g., PCI: qcom: Fix SDM845 incorrect register offset On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote: > In pcie_init_2_7_0 one of the register writes using incorrect offset > as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT > offset value should be 0x1A8 instead 0x178). > Update the correct offset value for SDM845 platform. Add "()" after function name. Add blank line between paragraphs. It'd be nice to have a clue about what fails because of the incorrect register offset. ed8cc3b1fc84 is almost two years old, so I guess it's not an obvious issue. > fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller") Capitalize "Fixes:", use 12-char SHA1, remove blank line after. Look at previous git history and copy the style there. > > Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> It looks like ed8cc3b1fc84 appeared in v5.6, so this should probably have a "Cc: stable@vger.kernel.org" tag as well. > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 8a7a300..5bce152 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > if (IS_ENABLED(CONFIG_PCI_MSI)) { > - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); > val |= BIT(31); > - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); > } > > return 0; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote: > In pcie_init_2_7_0 one of the register writes using incorrect offset > as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT > offset value should be 0x1A8 instead 0x178). > Update the correct offset value for SDM845 platform. > > fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller") > > Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> After incorporating the reviews from Bjorn H, Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 8a7a300..5bce152 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > if (IS_ENABLED(CONFIG_PCI_MSI)) { > - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); > val |= BIT(31); > - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); > } > > return 0; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
On 2021-10-21 13:06, Manivannan Sadhasivam wrote: > On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote: >> In pcie_init_2_7_0 one of the register writes using incorrect offset >> as per the platform register definitions >> (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT >> offset value should be 0x1A8 instead 0x178). >> Update the correct offset value for SDM845 platform. >> >> fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller") >> >> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> > > After incorporating the reviews from Bjorn H, > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Thanks, > Mani > Thanks Mani for the review. I will incorporate the changes as suggested by Bjorn H in next patch version. -Prasad >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >> b/drivers/pci/controller/dwc/pcie-qcom.c >> index 8a7a300..5bce152 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie >> *pcie) >> writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); >> >> if (IS_ENABLED(CONFIG_PCI_MSI)) { >> - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); >> + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); >> val |= BIT(31); >> - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); >> + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); >> } >> >> return 0; >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >> Forum, >> a Linux Foundation Collaborative Project >>
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8a7a300..5bce152 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); if (IS_ENABLED(CONFIG_PCI_MSI)) { - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); val |= BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); } return 0;
In pcie_init_2_7_0 one of the register writes using incorrect offset as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT offset value should be 0x1A8 instead 0x178). Update the correct offset value for SDM845 platform. fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller") Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)