From patchwork Fri May 15 09:59:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1290983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49NkQz3RdMz9sTc for ; Fri, 15 May 2020 19:59:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728260AbgEOJ7X (ORCPT ); Fri, 15 May 2020 05:59:23 -0400 Received: from mx.socionext.com ([202.248.49.38]:29843 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728142AbgEOJ7W (ORCPT ); Fri, 15 May 2020 05:59:22 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 15 May 2020 18:59:20 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 3264460057; Fri, 15 May 2020 18:59:20 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 15 May 2020 18:59:20 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id C404C1A12D0; Fri, 15 May 2020 18:59:19 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 3/5] dt-bindings: PCI: uniphier: Add iATU register description Date: Fri, 15 May 2020 18:59:01 +0900 Message-Id: <1589536743-6684-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589536743-6684-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1589536743-6684-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsis DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including